Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores - researchr publication authors

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Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna. Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores. In 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CA, USA. IEEE Computer Society, 2005. [doi]

This author has not been identified. Look up 'Ling Zhuo' in GoogleThis author has not been identified. Look up 'Gerald R. Morris' in GoogleThis author has not been identified. Look up 'Viktor K. Prasanna' in Google

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