Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores - researchr publication

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Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna. Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores. In 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CA, USA. IEEE Computer Society, 2005. [doi]

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