High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs

Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna. High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. IEEE Trans. Parallel Distrib. Syst., 18(10):1377-1392, 2007. [doi]

Abstract

Abstract is missing.