Sotirios G. Ziavras. Versatile Processor Design for Efficiency and High Performance. In 5th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2000), 7-10 December 2000, Dallas / Richardson, TX, USA. pages 266-273, IEEE Computer Society, 2000. [doi]
@inproceedings{Ziavras00,
title = {Versatile Processor Design for Efficiency and High Performance},
author = {Sotirios G. Ziavras},
year = {2000},
url = {http://csdl.computer.org/comp/proceedings/ispan/2000/0936/00/09360266abs.htm},
tags = {design},
researchr = {https://researchr.org/publication/Ziavras00},
cites = {0},
citedby = {0},
pages = {266-273},
booktitle = {5th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2000), 7-10 December 2000, Dallas / Richardson, TX, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-0936-3},
}