Christian G. Zoellin, Hans-Joachim Wunderlich. Low-power test planning for arbitrary at-speed delay-test clock schemes. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA. pages 93-98, IEEE Computer Society, 2010. [doi]
@inproceedings{ZoellinW10,
title = {Low-power test planning for arbitrary at-speed delay-test clock schemes},
author = {Christian G. Zoellin and Hans-Joachim Wunderlich},
year = {2010},
doi = {10.1109/VTS.2010.5469607},
url = {http://dx.doi.org/10.1109/VTS.2010.5469607},
tags = {testing},
researchr = {https://researchr.org/publication/ZoellinW10},
cites = {0},
citedby = {0},
pages = {93-98},
booktitle = {28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA},
publisher = {IEEE Computer Society},
isbn = {978-1-4244-6648-1},
}