Table of Contents

• The Era of Multi-core Chips -A Fresh Look on Software ChallengesGuang R. Gao. 1 [doi]
• Streaming Networks for Coordinating Data-Parallel Programs (Position Statement)Alexander V. Shafarenko. 2-5 [doi]
• Implementations of Square-Root and Exponential Functions for Large FPGAsMariusz Bajger, Amos Omondi. 6-23 [doi]
• Using Branch Prediction Information for Near-Optimal I-Cache LeakageSung Woo Chung, Kevin Skadron. 24-37 [doi]
• Scientific Computing Applications on the Imagine Stream ProcessorJing Du, Xuejun Yang, Guibin Wang, Fujiang Ao. 38-51 [doi]
• Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss DeterminationHaakon Dybdahl, Per Stenström. 52-66 [doi]
• A Study of the Performance Potential for Dynamic Instruction Hints SelectionRao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu. 67-80 [doi]
• Reorganizing UNIX for ReliabilityJorrit N. Herder, Herbert Bos, Ben Gras, Philip Homburg, Andrew S. Tanenbaum. 81-94 [doi]
• Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid ComputingChing-Hsien Hsu, Ming-Yuan Own, Kuan-Ching Li. 95-108 [doi]
• Processor Directed Dynamic Page PolicyDandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu. 109-122 [doi]
• Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time ApplicationsHuizhan Yi, Juan Chen, Xuejun Yang. 123-136 [doi]
• A Study on Transformation of Self-similar Processes with Arbitrary Marginal DistributionsHae-Duck Joshua Jeong, Jong-Suk Ruth Lee. 137-146 [doi]
• muTC - An Intermediate Language for Programming Chip MultiprocessorsChris R. Jesshope. 147-160 [doi]
• Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass DelaysLih Wen Koh, Oliver Diessel. 161-174 [doi]
• Trace-Based Data Cache Leakage Reduction at Link TimeLian Li 0002, Jingling Xue. 175-188 [doi]
• Parallelizing User-Defined and Implicit Reductions Globally on MultiprocessorsShih-Wei Liao. 189-202 [doi]
• Overload Protection for Commodity Network AppliancesLuke Macpherson. 203-218 [doi]
• An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional UnitFarhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue. 219-230 [doi]
• A High Performance Simulator System for a Multiprocessor System Based on a Multi-way ClusterArata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsunori Kubo. 231-243 [doi]
• Hardware Budget and Runtime System for Data-Driven Multithreaded Chip MultiprocessorKyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou. 244-259 [doi]
• Combining Wireless Sensor Network with Grid for Intelligent City TrafficFeilong Tang, Minglu Li, Chuliang Weng, Chongqing Zhang, Wenzhe Zhang, Hongyu Huang, Yi Wang. 260-269 [doi]
• A Novel Processor Architecture for Real-Time ControlXiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger Goodall, Tanya Vladimirova. 270-280 [doi]
• A 0-1 Integer Linear Programming Based Approach for Global Locality OptimizationsJun Xia, Li Luo, Xuejun Yang. 281-294 [doi]
• Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCsKang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil. 295-308 [doi]
• Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection NetworksTakashi Yokota, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba. 309-322 [doi]
• Design of an Efficient Flexible Architecture for Color Image EnhancementMing Z. Zhang, Li Tao, Ming-Jung Seow, Vijayan K. Asari. 323-336 [doi]
• Hypercube Communications on Optical Chordal Ring Networks with Chord Length of ThreeYawen Chen, Hong Shen, Haibo Zhang. 337-343 [doi]
• PMPS(3): A Performance Model of Parallel SystemsYong-ran Chen, Xing-yun Qi, Yue Qian, Wenhua Dou. 344-350 [doi]
• Issues and Support for Dynamic Register AllocationAbhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu. 351-358 [doi]
• A Heterogeneous Multi-core Processor Architecture for High Performance ComputingJianjun Guo, Kui Dai, Zhiying Wang. 359-365 [doi]
• Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock FormationMichael Hicks 0002, Colin Egan, Bruce Christianson, Patrick Quick. 366-372 [doi]
• Fault-Free Pairwise Independent Hamiltonian Paths on Faulty HypercubesSun-Yuan Hsieh. 373-379 [doi]
• Constructing Node-Disjoint Paths in Enhanced Pyramid NetworksHsien-Jone Hsieh, Dyi-Rong Duh. 380-386 [doi]
• Striping Cache: A Global Cache for Striped Network File SystemSheng-Kai Hung, Yarsun Hsu. 387-393 [doi]
• DTuplesHPC: Distributed Tuple Space for Desktop High Performance ComputingYi Jiang, Guangtao Xue, Minglu Li, Jinyuan You. 394-400 [doi]
• The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid MultiplierZhentao Li, Shuming Chen, Zhaoliang Li, Conghua Lei. 401-408 [doi]
• Live Range Aware Cache ArchitecturePeng Li, Dongsheng Wang, Songliu Guo, Tao Tian, Weimin Zheng. 409-415 [doi]
• The Challenges of Efficient Code-Generation for Massively Parallel ArchitecturesJason M. McGuiness, Colin Egan, Bruce Christianson, Guang Gao. 416-422 [doi]
• Reliable Systolic Computing Through RedundancyKunio Okuda, Siang Wun Song, Marcos Tatsuo Yamamoto. 423-429 [doi]
• A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor NetworksYantao Pan, Xicheng Lu, Peidong Zhu, Shen Ma. 430-436 [doi]
• A Context-Switch Reduction Heuristic for Power-Aware Off-Line SchedulingBiju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan. 437-444 [doi]
• On the Reliability of Drowsy Instruction CachesSoong Hyun Shin, Sung Woo Chung, Chu Shik Jhon. 445-451 [doi]
• Design of a Reconfigurable Cryptographic EngineKang Sun, Lingdi Ping, Jiebing Wang, Zugen Liu, Xuezeng Pan. 452-458 [doi]
• Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT ProcessorsCaixia Sun, Hongwei Tang, Minxuan Zhang. 459-465 [doi]
• The New BCD Subtractor and Its Reversible Logic ImplementationHimanshu Thapliyal, M. B. Srinivas. 466-472 [doi]
• Power-Efficient Microkernel of Embedded Operating System on ChipTianzhou Chen, Wei Hu, Yi Lian. 473-479 [doi]
• Understanding Prediction Limits Through Unbiased BranchesLucian N. Vintan, Arpad Gellert, Adrian Florea, Marius Oancea, Colin Egan. 480-487 [doi]
• Bandwidth Optimization of the EMCI for a High Performance 32-bit DSPDong Wang, Xiao Hu, Shuming Chen, Yang Guo. 488-494 [doi]
• Research on Petersen Graphs and Hyper-cubes Connected Interconnection NetworksWang Lei, Zhiping Chen. 495-501 [doi]
• Cycle Period Analysis and Optimization of Timed CircuitsLei Wang, Zhiying Wang, Kui Dai. 502-508 [doi]
• Acceleration Techniques for Chip-Multiprocessor Simulator DebugHaixia Wang, Dongsheng Wang, Peng Li. 509-515 [doi]
• A DDL-Based Software Architecture ModelMeiling Wang, Lei Liu. 516-522 [doi]
• Branch Behavior Characterization for Multimedia ApplicationsChia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen. 523-530 [doi]
• Optimization and Evaluating of StreamYGX2 on MASA Stream ProcessorMei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang. 531-537 [doi]
• SecureTorrent: A Security Framework for File SwarmingKenneth M. Wilson, Philip Machanick. 538-544 [doi]
• Register Allocation on Stream Processor with Local Register FileNan Wu, Mei Wen, Ju Ren, Yi He, Chunyuan Zhang. 545-551 [doi]
• A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer MaintenanceXiaofeng Wu, Tanya Vladimirova. 552-558 [doi]
• Compile-Time Thread Distinguishment Algorithm on VIM-Based ArchitectureXiaobo Yan, Xuejun Yang, Pu Wen. 559-566 [doi]
• Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-PipeliningJinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong. 567-573 [doi]
• Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia ApplicationsHoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim. 574-580 [doi]
• Automatic Synthesis of Interface Circuits from Simplified IP Interface ProtocolsChangRyul Yun, Younghwan Bae, Hanjin Cho, KyoungSon Jhang. 581-587 [doi]
• An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron MicroprocessorsChengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing. 588-594 [doi]
• An Efficient Approach to Energy Saving in MicrocontrollersWenhong Zhao, Feng Xia. 595-601 [doi]