Abstract is missing.
- From Code to ModelsGerard J. Holzmann. 3-10 [doi]
- Making Meaningful Models for Mere MortalJeff Kramer. 11-12 [doi]
- Overcoming Heterophobia: Modeling Concurrency in Heterogeneous SystemsJerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli. 13 [doi]
- Correct Performance of Transaction CapabilitiesThomas Arts, Izak van Langevelde. 35-42 [doi]
- Analysis of Performance Limitations in Multithreaded Multiprocessor ArchitecturesWlodzimierz M. Zuberek. 43-52 [doi]
- Abstracting from Failure ProbabilitiesJan Jürjens. 53 [doi]
- Algorithms for Signal and Message Asynchronous Communication Mechanisms and Their AnalysisFei Xia, Ian G. Clark. 65 [doi]
- Property Preserving Transition Refinement with Concurrent Runs: An ExampleSibylle Peuker. 77-86 [doi]
- Implementing Communicating Processes in the Event of Interface DifferenceJonathan Burton, Maciej Koutny, Giuseppe Pappalardo. 87 [doi]
- From Formal Specifications to Ready-to-Use Software Components: The Concurrent Object Oriented Petri Net ApproachStanislav Chachkov, Didier Buchs. 99 [doi]
- A Petri Net Meta-Model to Develop Software Components for Embedded SystemsRicardo Jorge Machado, João M. Fernandes. 113-122 [doi]
- Strength and Weaknesses of Genetic List Scheduling for Heterogeneous SystemsMartin Grajcar. 123-132 [doi]
- Software Implementation of Synchronous ProgramsCharles Andre, Frédéric Boulanger, Alain Girault. 133-142 [doi]
- Embedding Imperative Synchronous Languages in Interactive Theorem ProversKlaus Schneider. 143 [doi]
- A structural encoding technique for the synthesis of asynchronous circuitsJosep Carmona, Jordi Cortadella, Enric Pastor. 157-166 [doi]
- Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter EstimationOscar Garnica, Juan Lanchares, Román Hermida. 167-178 [doi]
- Towards Synthesis of Monotonic Asynchronous Circuits from Signal Transition GraphsNikolai Starodoubtsev, Sergei Bystrov, Michael V. Goncharov, Ilya V. Klotchkov, Alexander B. Smirnov. 179-188 [doi]
- Semi-Hiding Operators and the Analysis of Active-Edge Specifications for Digital CircuitsRadu Negulescu, Xiaohua Kong. 189 [doi]
- Exploration TestingJuhana Helovuo, Sari Leppänen. 201-210 [doi]
- Exploiting Stabilizers and Parallelism in State Space Generation with the Symmetry MethodLouise Lorentsen, Lars Michael Kristensen. 211-220 [doi]
- Automata Generation for On-the-fly Automatic Verification Using Formulas of an Interval LogicMiguel J. Hornos, Manuel I. Capel. 221-230 [doi]
- The BDD Space Complexity of Different Forms of ConcurrencyMichael Baldamus, Klaus Schneider. 231 [doi]
- Synthesis of Net Systems with Inhibitor Arcs from Step Transition SystemsMarta Pietkiewicz-Koutny. 245-254 [doi]