Table of Contents

• Approximate FPGA-Based LSTMs Under Computation Time ConstraintsMichalis Rizakis, Stylianos I. Venieris, Alexandros Kouris, Christos-Savvas Bouganis. 3-15 [doi]
• Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet ClassificationJiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung. 16-28 [doi]
• Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable LogicJiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung. 29-42 [doi]
• Deep Learning on High Performance FPGA Switching Boards: Flow-in-CloudKazusa Musha, Tomohiro Kudoh, Hideharu Amano. 43-54 [doi]
• SqueezeJet: High-Level Synthesis Accelerator Design for Deep Convolutional Neural NetworksPanagiotis G. Mousouliotis, Loukas P. Petrou. 55-66 [doi]
• Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative FilteringKonstantinos Katsantonis, Christoforos Kachris, Dimitrios Soudris. 67-78 [doi]
• VerCoLib: Fast and Versatile Communication for FPGAs via PCI ExpressOguzhan Sezenlik, Sebastian Schüller, Joachim K. Anlauf. 81-92 [doi]
• Lookahead Memory Prefetching for CGRAs Using Partial Loop UnrollingLukas Johannes Jung, Christian Hochberger. 93-104 [doi]
• Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural NetworkKalindu Herath, Alok Prakash, Thambipillai Srikanthan. 105-118 [doi]
• Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-designFarhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan. 119-131 [doi]
• FPGA-Based Memory Efficient Shift-And Algorithm for Regular Expression MatchingJunsik Kim, Jaehyun Park. 132-141 [doi]
• Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary StudyKazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano. 142-150 [doi]
• An FPGA/HMC-Based Accelerator for Resolution Proof CheckingTim Hansmeier, Marco Platzner, David Andrews. 153-165 [doi]
• An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization AlgorithmAlmabrok Abdoalnasir, Mihalis Psarakis, Anastasios I. Dounis. 166-177 [doi]
• ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCsSanthi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy. 178-191 [doi]
• FPGA-Based Parallel Pattern MatchingMasahiro Fukuda, Yasushi Inoguchi. 192-203 [doi]
• Embedded Vision Systems: A Review of the LiteratureDeepayan Bhowmik, Kofi Appiah. 204-216 [doi]
• A Survey of Low Power Design Techniques for Last Level CachesEmmanuel Ofori-Attah, Xiaohang Wang, Michael Opoku Agyeman. 217-228 [doi]
• ISA-DTMR: Selective Protection in Configurable Heterogeneous MulticoresAugusto G. Erichsen, Anderson Luiz Sartor, Jeckson Dellagostin Souza, Monica Magalhães Pereira, Stephan Wong, Antonio C. S. Beck. 231-242 [doi]
• Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft ErrorsFabio Benevenuti, Fernanda Lima Kastensmidt. 243-254 [doi]
• High Performance UDP/IP 40Gb Ethernet Stack for FPGAsMilind Parelkar, Darshan Jetly. 255-268 [doi]
• Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway ApproachChristos P. Antonopoulos, Konstantinos Antonopoulos, Christos Panagiotou, Nikolaos S. Voros. 269-280 [doi]
• A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor NetworksBruno da Silva, Laurent Segers, An Braeken, Kris Steenhaut, Abdellah Touhafi. 281-293 [doi]
• A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip SensingLampros Pyrgas, Paris Kitsos. 294-303 [doi]
• HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core EraRaheel Afsharmazayejani, Fahimeh Yazdanpanah, Amin Rezaei, Mohammad Alaei, Masoud Daneshtalab. 304-316 [doi]
• Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing ApproachLuca Sterpone, Ludovica Bozzoli. 319-330 [doi]
• A Dynamic Partial Reconfigurable Overlay Framework for PythonBenedikt Janßen, Florian Kästner, Tim Wingender, Michael Hübner. 331-342 [doi]
• Runtime Adaptive Cache for the LEON3 ProcessorOsvaldo Navarro, Michael Hübner. 343-354 [doi]
• Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable ArchitectureRafael Fão de Moura, Michael Guilherme Jordan, Antonio Carlos Schneider Beck, Mateus Beck Rutzig. 355-366 [doi]
• DIM-VEX: Exploiting Design Time Configurability and Runtime ReconfigurabilityJeckson Dellagostin Souza, Anderson Luiz Sartor, Luigi Carro, Mateus Beck Rutzig, Stephan Wong, Antonio C. S. Beck. 367-378 [doi]
• The Use of HACP+SBT Lossless Compression in Optimizing Memory Bandwidth Requirement for Hardware Implementation of Background Modelling AlgorithmsKamil Piszczek, Piotr Janus, Tomasz Kryjak. 379-391 [doi]
• A Reconfigurable PID ControllerSikandar Khan, Kyprianos Papadimitriou, Giorgio C. Buttazzo, Kostas Kalaitzakis. 392-403 [doi]
• High-Level Synthesis of Software-Defined MPSoCsJens Rettkowski, Diana Goehringer. 407-419 [doi]
• Improved High-Level Synthesis for Complex CellML ModelsBjörn Liebig, Julian Oppermann, Oliver Sinnen, Andreas Koch 0001. 420-432 [doi]
• An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded ProcessorsHabib ul Hasan Khan, Ahmed Kamal, Diana Goehringer. 433-445 [doi]
• Rapid Prototyping and Verification of Hardware Modules Generated Using HLSJulian Caba, João M. P. Cardoso, Fernando Rincón, Julio Dondo, Juan Carlos López. 446-458 [doi]
• Comparing C and SystemC Based HLS Methods for Reconfigurable Systems DesignKonstantinos Georgopoulos, Pavlos Malakonakis, Nikolaos Tampouratzis, Antonis Nikitakis, Grigorios Chrysos, Apostolos Dollas, Dionysios N. Pnevmatikatos, Ioannis Papaefstathiou. 459-470 [doi]
• Fast DSE for Automated Parallelization of Embedded Legacy ApplicationsKris Heid, Jakob Wenzel 0002, Christian Hochberger. 471-484 [doi]
• Control Flow Analysis for Embedded Multi-core Hybrid SystemsAugusto W. Hoppe, Fernanda Lima Kastensmidt, Jürgen Becker. 485-496 [doi]
• A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAsPedro Henrique Exenberger Becker, Anderson Luiz Sartor, Marcelo Brandalero, Tiago Trevisan Jost, Stephan Wong, Luigi Carro, Antonio C. S. Beck. 499-510 [doi]
• A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G SystemsMário Lopes Ferreira, João Canas Ferreira, Michael Hübner. 511-522 [doi]
• Area-Energy Aware Dataflow Optimisation of Visual Tracking SystemsPaulo Garcia, Deepayan Bhowmik, Andrew M. Wallace, Robert J. Stewart, Greg Michaelson. 523-536 [doi]
• Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAsAyan Palchaudhuri, Anindya Sundar Dhar. 537-550 [doi]
• Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent OptimizationsUmar Ibrahim Minhas, Roger W. Woods, George Karakonstantis. 551-563 [doi]
• ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short ReadsSanthi Natarajan, N. Krishna Kumar, H. V. Anuchan, Debnath Pal, S. K. Nandy. 564-577 [doi]
• An OpenCLTM Implementation of WebP Accelerator on FPGAsZhenhua Guo, Baoyu Fan, Yaqian Zhao, Xuelei Li, Shixin Wei, Long Li. 578-589 [doi]
• Efficient Multitasking on FPGA Using HDL-Based CheckpointingHoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima. 590-602 [doi]
• High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable HardwareUzaif Sharif, Shahnam Mirzaei. 603-614 [doi]
• Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing SystemsJohannes Pfau, Shalina Percy Delicia Figuli, Steffen Bähr, Jürgen Becker. 615-626 [doi]
• Reconfigurable IP-Based Spectral Interference CancellerPeter Littlewood, Shahnam Mirzaei, Krishna Murthy Kattiyan Ramamoorthy. 627-639 [doi]
• FPGA-Assisted Distribution Grid SimulatorNikolaos Tzanis, Grigorios Proiskos, Michael K. Birbas, Alexios N. Birbas. 640-646 [doi]
• Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy TradeoffsGennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Alberto Bosio. 647-658 [doi]
• CGRA Tool Flow for Fast Run-Time ReconfigurationFlorian Fricke, André Werner, Keyvan Shahin, Michael Hübner. 661-672 [doi]
• Seamless FPGA Deployment over Spark in Cloud Computing: A Use Case on Machine Learning Hardware AccelerationChristoforos Kachris, Ioannis Stamelos, Elias Koromilas, Dimitrios Soudris. 673-684 [doi]
• The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical ApplicationsJürgen Becker, Falco K. Bapp. 685-699 [doi]
• Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO ApproachPanayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller 0005, Umut Durak, Jürgen Becker. 700-711 [doi]
• Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO ExperienceChristos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner, Fynn Schwiegelshohn, Diana Goehringer, Maria Dagioglou, Georgios Stavrinos, Stasinos Konstantopoulos, Vangelis Karkaletsis. 712-723 [doi]
• HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALEPavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou, Luciano Lavagno, Ioannis Papaefstathiou, Iakovos Mavroidis. 724-736 [doi]
• Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An OverviewAhmad Sadek, Ananya Muddukrishna, Lester Kalms, Asbjørn Djupdal, Ariel Podlubne, Antonio Paolillo, Diana Goehringer, Magnus Jahre. 737-749 [doi]