Abstract is missing.
- Fast Approximation of the Top-k Items in Data Streams Using a Reconfigurable AcceleratorAli Ebrahim, Jalal Khalifat. 3-17 [doi]
- Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed DatabasesJohannes Wirth, Jaco A. Hofmann, Lasse Thostrup, Andreas Koch 0001, Carsten Binnig. 18-32 [doi]
- Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGAJohannes Pfau, Peter Wagih Zaki, Jürgen Becker 0001. 35-49 [doi]
- Timing Optimization for Virtual FPGA ConfigurationsLinus Witschen, Tobias Wiersema, Masood Raeisi Nafchi, Arne Bockhorn, Marco Platzner. 50-64 [doi]
- Hardware Based Loop Optimization for CGRA ArchitecturesChilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy. 65-80 [doi]
- Supporting On-Chip Dynamic Parallelism for Task-Based Hardware AcceleratorsCarsten Heinz, Andreas Koch 0001. 81-92 [doi]
- Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable PlatformsJörg Keller 0001, Sebastian Litzinger, Christoph W. Kessler. 93-107 [doi]
- Task-Based Programming Models for Heterogeneous Recurrent WorkloadsJaume Bosch, Miquel Vidal, Antonio Filgueras, Daniel Jiménez-González, Carlos Álvarez 0001, Xavier Martorell, Eduard Ayguadé. 108-122 [doi]
- Multi-layered NoCs with Adaptive Routing for Mixed Criticality SystemsNidhi Anantharajaiah, Zhe Zhang, Jürgen Becker 0001. 125-139 [doi]
- PDU Normalizer Engine for Heterogeneous In-Vehicle Networks in Automotive GatewaysAngela Gonzalez Mariño, Francesc Fons, Li Ming, Juan-Manuel Moreno Aróstegui. 140-155 [doi]
- StreamGrid - An AXI-Stream-Compliant Overlay ArchitectureChristopher Blochwitz, León Philipp, Mladen Berekovic, Thilo Pionteck. 156-170 [doi]
- Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based ReconfigurationAli Asghar, Benjamin Hettwer, Emil Karimov, Daniel Ziener. 173-187 [doi]
- Moving Target and Implementation Diversity Based Countermeasures Against Side-Channel AttacksNadir Khan, Benjamin Hettwer, Jürgen Becker 0001. 188-202 [doi]
- Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable PlatformRanda Zarrouk, Saleh Mulhem, Wael Adi, Mladen Berekovic. 203-217 [doi]
- Transparent Near-Memory Computing with a Reconfigurable ProcessorFabian Lesniak, Fabian Kreß, Jürgen Becker 0001. 221-231 [doi]
- A Dataflow Architecture for Real-Time Full-Search Block Motion EstimationJesús Barba, Julián Caba, Soledad Escolar, Jose A. de la Torre, Fernando Rincón, Juan C. López. 232-241 [doi]
- Providing Tamper-Secure SoC Updates Through Reconfigurable HardwareFranz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich. 242-253 [doi]
- Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive ApplicationsAshutosh Dhar, Paul Reckamp, Jinjun Xiong, Wen-mei Hwu, Deming Chen. 254-264 [doi]
- Dynamic Spatial Multiplexing on FPGAs with OpenCLPascal Jungblut, Dieter Kranzlmüller. 265-274 [doi]
- Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPUHector Gerardo Muñoz Hernandez, Mitko Veleski, Marcelo Brandalero, Michael Hübner 0001. 275-284 [doi]
- Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance ComputingArjun Ramaswami, Tobias Kenter, Thomas D. Kühne, Christian Plessl. 285-294 [doi]
- FPGA Implementation of Custom Floating-Point Logarithm and DivisionNelson Campos, Slava Chesnokov, Eran Edirisinghe, Alexis Lluis. 295-304 [doi]
- On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial ReconfigurationMuhammad Irfan 0004, Kizheppatt Vipin, Ray C. C. Cheung. 305-314 [doi]
- Domain-Specific Modeling and Optimization for Graph Processing on FPGAsMohamed W. Hassan, Peter M. Athanas, Yasser Y. Hanafy. 315-326 [doi]
- Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud Using X-RaysDimitrios Danopoulos, Christoforos Kachris, Dimitrios Soudris. 327-336 [doi]