Abstract is missing.
- SNN vs. CNN Implementations on FPGAs: An Empirical EvaluationPatrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze. 3-18 [doi]
- Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware TrainingOlle Hansson, Mahdieh Grailoo, Oscar Gustafsson, José L. Núñez-Yáñez. 33-47 [doi]
- Reconfigurable Edge Hardware for Intelligent IDS: Systematic ApproachWadid Foudhaili, Anouar Nechi, Celine Thermann, Mohammad Al Johmani, Rainer Buchty, Mladen Berekovic, Saleh Mulhem. 48-62 [doi]
- Bridging the Gap in ECG Classification: Integrating Self-supervised Learning with Human-in-the-Loop Amid Medical Equipment Hardware ConstraintsGuilherme Silva 0006, Pedro Silva 0004, Gladston Moreira, Eduardo Luz 0001. 63-74 [doi]
- Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance ComputingTorben Kalkhof, Carsten Heinz, Andreas Koch 0001. 75-89 [doi]
- Cryptographic Security Through a Hardware Root of TrustLuis F. Rojas-Muñoz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Eros Camacho-Ruiz, Pablo Navarro-Torrero, Apurba Karmakar, Carlos Fernández García, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Pau Ortega-Castro, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández, Piedad Brox. 106-119 [doi]
- Graphtoy: Fast Software Simulation of Applications for AMD's AI EnginesJonathan Strobl, Leonardo Solis-Vasquez, Yannick Lavan, Andreas Koch 0001. 166-180 [doi]
- A DSL and MLIR Dialect for Streaming and VectorisationManuel Cerqueira da Silva, Luís Miguel Sousa, Nuno Paulino 0001, João Bispo. 181-190 [doi]
- Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ DevicesBardia Babaei, Dirk Koch. 193-209 [doi]
- High Performance Connected Components Accelerator for Image Processing in the EdgeJosé L. Mira, Jesús Barba, Julián Caba, Jose A. de la Torre, Fernando Rincón, Soledad Escolar, Juan Carlos López 0001. 210-221 [doi]
- Trusted Computing Architectures for IoT DevicesAn Braeken, Bruno da Silva 0001, Laurent Segers, Johannes Knödtel, Marc Reichenbach, Cornelia Wulf, Sergio A. Pertuz 0001, Diana Göhringer, Jo Vliegen, Md Masoom Rabbani, Nele Mentens. 241-254 [doi]
- A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed ComputingSergio A. Pertuz 0001, Cornelia Wulf, Najdet Charaf, Lester Kalms, Diana Göhringer. 267-281 [doi]
- A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece AcceleratorVatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández 0001. 282-295 [doi]