Abstract is missing.
- Locality: The 3rd Wall and the Need for Innovation in Parallel ArchitecturesPeter M. Kogge, Brian A. Page. 3-18 [doi]
- Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time TasksThomas Carle, Hugues Cassé. 19-34 [doi]
- Transparent Resilience for Approximate DRAMJoão Fabrício Filho, Isaías B. Felzmann, Lucas Francisco Wanner. 35-50 [doi]
- Automatic Mapping of Parallel Pattern-Based Algorithms on Heterogeneous ArchitecturesLukas Trümper, Julian Miller, Christian Terboven, Matthias S. Müller. 53-67 [doi]
- Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control SystemsAlejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Javier de Lasala, Ion Larrañaga. 68-83 [doi]
- DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution ModelRoberto Giorgi, Marco Procaccini, Amin Sahebi. 84-100 [doi]
- Performance Gain of a Data Flow Oriented ISA as Replacement for Java BytecodeAlexander Schwarz, Christian Hochberger. 103-117 [doi]
- Towards Transparent Dynamic Binary Translation from RISC-V to a CGRARamon Wirsch, Christian Hochberger. 118-132 [doi]
- An Organic Computing System for Automated TestingLukas Rosenbauer, David Pätzel, Anthony Stein, Jörg Hähner. 135-149 [doi]
- Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone SystemEric Hutter, Uwe Brinkschulte. 150-164 [doi]
- Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-core MCUsFabio Montagna, Giuseppe Tagliavini, Davide Rossi, Angelo Garofalo, Luca Benini. 167-182 [doi]
- Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-GatingWilliam B. Toms, John Goodacre, Mikel Luján. 183-198 [doi]
- BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error DetectionChristian Schulz-Hanke. 201-212 [doi]
- Evaluating Soft Error Mitigation Trade-offs During Early Design StagesHao Qiu, Bor-Tyng Lin, Semiu A. Olowogemo, William H. Robinson, Daniel B. Limbrick. 213-228 [doi]