Abstract is missing.
- CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural NetworksYuanfang Li, Ardavan Pedram. 1-10 [doi]
- A message from the general chair and program chairKen Eguro, Ryan Kastner. 1 [doi]
- Fast and efficient implementation of Convolutional Neural Networks on FPGAAbhinav Podili, Chi Zhang, Viktor K. Prasanna. 11-18 [doi]
- Parallel Multi Channel convolution using General Matrix MultiplicationAravind Vasudevan, Andrew Anderson, David Gregg. 19-24 [doi]
- High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component AnalysisMahdi Nazemi, Shahin Nazarian, Massoud Pedram. 25-28 [doi]
- Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPSBikash Poudel, Naresh Kumar Giri, Arslan Munir. 29-36 [doi]
- High-Level Synthesis for side-channel defenseS. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong. 37-44 [doi]
- DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacksAmin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran. 45-52 [doi]
- Hardwiring the OS kernel into a Java application processorChun-Jen Tsai, Cheng-Ju Lin, Cheng-Yang Chen, Yan-Hung Lin, Wei-Jhong Ji, Sheng-Di Hong. 53-60 [doi]
- Hardware support for embedded operating system securityArman Pouraghily, Tilman Wolf, Russell Tessier. 61-66 [doi]
- Hardware-accelerated CCD readout smear correction for Fast Solar PolarimeterStefan Tabel, Korbinian Weikl, Walter Stechele. 67-74 [doi]
- Real-time object detection in software with custom vector instructions and algorithm changesJoe Edwards, Guy G. F. Lemieux. 75-82 [doi]
- An efficient embedded multi-ported memory architecture for next-generation FPGAsS. Navid Shahrouzi, Darshika G. Perera. 83-90 [doi]
- A Staged Memory Resource Management Method for CMP systemsYangguo Liu, Junlin Lu, Dong Tong, Xu Cheng. 91-98 [doi]
- CFStore: Boosting Hybrid storage performance by device crossfireWei Zhou, Dan Feng, Zhipeng Tan. 99-106 [doi]
- RVNet: A fast and high energy efficiency network packet processing system on RISC-VYanpeng Wang, Mei Wen, Chunyuan Zhang, Jie Lin. 107-110 [doi]
- Massive spatial query on the Kepler architectureYili Gong, Jia Tang, Wenhai Li, Zihui Ye. 111-118 [doi]
- PFSI.sw: A programming framework for sea ice model algorithms based on Sunway many-core processorBinyang Li, Bo Li, Depei Qian. 119-126 [doi]
- MicRun: A framework for scale-free graph algorithms on SIMD architecture of the Xeon PhiJie Lin, Qingbo Wu, Yusong Tan, Jie Yu, Qi Zhang, Xiaoling Li, Lei Luo. 127-136 [doi]
- Hierarchical Dataflow Model for efficient programming of clustered manycore processorsJulien Hascoet, Karol Desnos, Jean-François Nezan, Benoît Dupont de Dinechin. 137-142 [doi]
- Modeling and evaluation for gather/scatter operations in Vector-SIMD architecturesHongbing Tan, Haiyan Chen, Sheng Liu, Jianguo Wu. 143-148 [doi]
- reMinMin: A novel static energy-centric list scheduling approach based on real measurementsAchim Lösch, Marco Platzner. 149-154 [doi]
- Hardware design and analysis of efficient loop coarsening and border handling for image processingM. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich. 155-163 [doi]
- High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extensionRishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual. 164-169 [doi]
- Design and implementation of adaptive signal processing systems using Markov decision processesLin Li, Adrian E. Sapio, Jiahao Wu, Yanzhou Liu, Kyunghun Lee, Marilyn Wolf, Shuvra S. Bhattacharyya. 170-175 [doi]
- An embedded scalable linear model predictive hardware-based controller using ADMMPei Zhang, Joseph Zambreno, Phillip H. Jones. 176-183 [doi]
- CGRA-ME: A unified framework for CGRA modelling and explorationS. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin-Hee Kim, Yuko Hara-Azumi, Jason Anderson. 184-189 [doi]
- OpenCL-based design pattern for line rate packet processingJehandad Khan, Peter Athanas, Skip Booth, John Marshall. 190-194 [doi]
- Acceleration of Frequent Itemset Mining on FPGA using SDAccel and Vivado HLSVinh Dang, Kevin Skadron. 195-200 [doi]
- OpenMP device offloading to FPGA acceleratorsLukas Sommer, Jens Korinth, Andreas Koch 0001. 201-205 [doi]
- DeepPump: Multi-pumping deep Neural NetworksRuizhe Zhao, Tim Todman, Wayne Luk, Xinyu Niu. 206 [doi]
- Efficiency in ILP processing by using orthogonalityMarcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich. 207 [doi]
- A fast and accurate logarithm accelerator for scientific applicationsJing Chen, Xue Liu. 208 [doi]
- Model checking cloud rendering system for the QoS evaluationHaoyu Liu, Huahu Xu, Honghao Gao, Danqi Chu. 209 [doi]
- High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithmsYuanhong Huo, Dake Liu. 210 [doi]
- KV-FTL: A novel key-value based FTL scheme for large scale SSDsJuan Li, Zhengguo Chen, Zhiguang Chen, Nong Xiao, Fang Liu. 211 [doi]