Table of Contents

• Preface ASAP 2023João M. P. Cardoso, Alexandra Jimborean, Nele Mentens, José Gabriel F. Coutinho. [doi]
• A Novel FPGA-Based Circuit Simulator for Accelerating Reinforcement Learning-Based Design of Power ConvertersZhenyu Xu, Miaoxiang Yu, Jillian Cai, Qing Yang 0001, Yeonho Jeong, Tao Wei. 1-9 [doi]
• Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum CryptographyYifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han 0003. 10-17 [doi]
• SONA: An Accelerator for Transform-Domain Neural Networks with Sparse-Orthogonal WeightsPierre Abillama, Zichen Fan, Yu Chen 0070, Hyochan An, Qirui Zhang 0001, Seungkyu Choi, David T. Blaauw, Dennis Sylvester, Hun-Seok Kim. 18-26 [doi]
• COIN: Combinational Intelligent NetworksIgor D. S. Miranda, Aman Arora, Zachary Susskind, Josias S. A. Souza, Mugdha P. Jadhao, Luis A. Q. Villon, Diego L. C. Dutra, Priscila M. V. Lima, Felipe M. G. França, Maurício Breternitz, Lizy K. John. 27-28 [doi]
• A Heterogeneous Computer Architecture Accelerating Reinforcement Learning-based Design for Silicon Photonic DevicesMiaoxiang Yu, Zhenyu Xu, Jillian Cai, Qing Yang 0001, Tao Wei. 29-30 [doi]
• Audio DSP to FPGA CompilationMaxime Popoff, Romain Michon, Tanguy Risset, Pierre Cochard, Stéphane Letz, Yann Orlarey, Florent de Dinechin. 31-32 [doi]
• Mayalok: A Cyber-Deception Hardware Using Runtime Instruction InfusionPreet Derasari, Kailash Gogineni, Guru Venkataramani. 33-40 [doi]
• A Suite of Division Algorithms for Posit ArithmeticRaul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella. 41-44 [doi]
• PreCog: Near-Storage Accelerator for Heterogeneous CNN InferenceJiyoung An, Esmerald Aliaj, Sang-Woo Jun. 45-52 [doi]
• iKnowFirst: An Efficient DPU-Assisted Compaction for LSM-Tree-Based Key-Value StoresJiahong Chen, Shengzhe Wang, Zhihao Zhang, Suzhen Wu, Bo Mao. 53-60 [doi]
• Exploiting Subword Permutations to Maximize CNN Compute Performance and EfficiencyMichael Beyer, Sven Gesper, Andre Guntoro, Guillermo Payá Vayá, Holger Blume. 61-68 [doi]
• Efficient 1D Grouped Convolution for PyTorch a Case Study: Fast On-Device Fine-Tuning for SqueezeBERTSeyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer. 69-75 [doi]
• FAWS: FPGA Acceleration of Large-Scale Wave SimulationsDimitrios Gourounas, Bagus Hanindhito, Arash Fathi, Dimitar Trenev, Lizy K. John, Andreas Gerstlauer. 76-84 [doi]
• Boomerang: Physical-Aware Design Space Exploration Framework on RISC-V SonicBOOM MicroarchitectureYen-Fu Liu, Chou-Ying Hsieh, Sy-Yen Kuo. 85-93 [doi]
• Supporting RISC-V Performance Counters Through Linux Performance Analysis ToolsJoao Mario Domingos, Tiago Rocha, Nuno Neves 0002, Nuno Roma, Pedro Tomás, Leonel Sousa. 94-101 [doi]
• Co-Design of Algorithm and FPGA Accelerator for Conditional Independence TestCe Guo, Wayne Luk, Alexander Warren, Joshua M. Levine, Peter Brookes. 102-109 [doi]
• FieldHAR: A Fully Integrated End-to-End RTL Framework for Human Activity Recognition with Neural Networks from Heterogeneous SensorsMengxi Liu, Bo Zhou 0005, Zimin Zhao, Hyeonseok Hong, Hyun Kim, Sungho Suh, Vítor Fortes Rey, Paul Lukowicz. 110-118 [doi]
• FMM-X3D: FPGA-Based Modeling and Mapping of X3D for Human Action RecognitionPetros Toupas, Christos-Savvas Bouganis, Dimitrios Tzovaras. 119-126 [doi]
• GPU Acceleration of Multi-Object Tracking with Motion Vector Interpolation and Affine TransformationYoshiki Kunimoto, Qiong Chang, Yoshiki Yamaguchi, Tsutomu Maruyama. 127-134 [doi]
• Real-Time and Approximate Iterative Optical Flow Implementation on Low-Power Embedded CPUsMaxime Millet, Adrien Cassagne, Nicolas Rambaux, Lionel Lacassagne. 135-138 [doi]
• Real-Time Zero-Day Intrusion Detection System for Automotive Controller Area Network on FPGAsShashwat Khandelwal, Shanker Shreejith. 139-146 [doi]
• Resource-Constrained Encryption: Extending Ibex with a QARMA Hardware AcceleratorMathijs De Kremer, Marco Brohet, Subhadeep Banik, Roberto Avanzi, Francesco Regazzoni 0001. 147-155 [doi]
• SieveMem: A Computation-in-Memory Architecture for Fast and Accurate Pre-AlignmentTaha Shahroodi, Michael Miao, Mahdi Zahedi, Stephan Wong, Said Hamdioui. 156-164 [doi]
• An FFT Accelerator Using Deeply-coupled RISC-V Instruction Set Extension for Arbitrary Number of PointsShijie Jiang, Yi Zou, Hao Wang, Wanwan Li. 165-171 [doi]
• FarSlayer: Turnkey Acceleration of Legacy Software on Commodity FPGA CardsEsmerald Aliaj, Alberto Krone-Martins, Joshua Garcia, Sang-Woo Jun. 172-179 [doi]
• An Efficient Accelerator for Nonlinear Model Predictive ControlSergio A. Pertuz 0001, Ariel Podlubne, Diana Goehringer. 180-187 [doi]
• Oikonomos: An Opportunistic, Deep-Learning, Resource-Recommendation System for Cloud HPCJan-Harm L. F. Betting, Dimitrios Liakopoulos, Max C. W. Engelen, Christos Strydis. 188-196 [doi]
• HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level SynthesisZhigang Wei, Aman Arora, Ruihao Li 0002, Lizy K. John. 197-204 [doi]
• AccMER: Accelerating Multi-Agent Experience Replay with Cache Locality-Aware PrioritizationKailash Gogineni, Yongsheng Mei, Tian Lan, Peng Wei, Guru Venkataramani. 205-212 [doi]
• SimPyler: A Compiler-Based Simulation Framework for Machine Learning AcceleratorsYannick Braatz, Dennis Sebastian Rieber, Taha Soliman, Oliver Bringmann 0001. 213-220 [doi]