Abstract is missing.
- Keynote: Variation-tolerant adaptive and resilient designs in nanoscale CMOSVivek De. [doi]
- Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply VoltagesJian Liu, Steven M. Nowick, Mingoo Seok. 1-7 [doi]
- A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection SystemsNaoya Onizawa, Warren J. Gross, Takahiro Hanyu. 8-15 [doi]
- Capacitor Discharging Through Asynchronous Circuit SwitchingReza Ramezani, Alex Yakovlev. 16-22 [doi]
- Modular Redundancy in a GALS System Using Asynchronous Recovery LinksJakob Lechner, Varadan Savulimedu Veeravalli. 23-30 [doi]
- An SET Tolerant Tree Arbiter CellSyed Rameez Naqvi, Andreas Steininger, Jakob Lechner. 31-39 [doi]
- NanoMesh: An Asynchronous Kilo-Core System-on-ChipJonathan Tse, Andrew Lines. 40-49 [doi]
- An Asynchronous Dataflow Signal Processing Architecture to Minimize Energy per OpBo Marr, Julia Karl, Lloyd Lewins, Ken Prager, Dan Thompson. 50-57 [doi]
- cellTK: Automated Layout for Asynchronous Circuits with Nonstandard CellsRobert Karmazin, Carlos Tadeo Ortega Otero, Rajit Manohar. 58-66 [doi]
- Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based SimulationEslam Yahya, Laurent Fesquet, Yehea Ismail, Marc Renaudin. 67-74 [doi]
- Deriving Performance Bounds for Conditional Asynchronous Circuits Using Linear ProgramingMehrdad Najibi, Peter A. Beerel. 75-82 [doi]
- GALS Design for Spectral Peak Attenuation of Switching CurrentXin Fan, Oliver Schrape, Miroslav Marinkovic, Peter Dahnert, Milos Krstic, Eckhard Grass. 83-90 [doi]
- Distributed Phase Correction TechniqueSuwen Yang, Frankie Y. Liu. 91-98 [doi]
- A Self-Timed Ring Based True Random Number GeneratorAbdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet. 99-106 [doi]
- SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay OverheadShomit Das, Vikas S. Vij, Kenneth S. Stevens. 107-114 [doi]
- Classifying Virtual Channel Access Control Schemes for Asynchronous NoCsRobert Najvirt, Syed Rameez Naqvi, Andreas Steininger. 115-123 [doi]
- A Bit of Analysis on Self-Timed Single-Bit On-Chip LinksJonathan Tse, Benjamin Hill, Rajit Manohar. 124-133 [doi]
- Can QDI Combinational Circuits be Implemented without C-elements?Fu-Chiung Cheng, Chi Chen. 134-141 [doi]
- Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI TechnologyJeremie Hamon, Edith Beigné. 142-149 [doi]
- Inverting Martin Synthesis for VerificationStephen Longfield Jr., Rajit Manohar. 150-157 [doi]
- MTBF Bounds for Multistage SynchronizersSalomon Beer, Jerome Cox, Tom Chaney, David M. Zar. 158-165 [doi]
- MTBF Estimation in Coherent Clock DomainsSalomon Beer, Ran Ginosar, Rostislav (Reuven) Dobkin, Yoav Weizman. 166-173 [doi]
- An Approach for Efficient Metastability Characterization of FPGAs through the DesignerThomas Polzer, Andreas Steininger. 174-182 [doi]
- Formal Deadlock Verification for Click CircuitsFreek Verbeek, Sebastiaan J. C. Joosten, Julien Schmaltz. 183-190 [doi]
- Unfaithful Glitch Propagation in Existing Binary Circuit ModelsMatthias Függer, Thomas Nowak, Ulrich Schmid. 191-199 [doi]