Abstract is missing.
- A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word StructureNaoya Onizawa, Shoun Matsunaga, Takahiro Hanyu. 1-8 [doi]
- An Asynchronous SDM Network-on-Chip Tolerating Permanent FaultsGuangda Zhang, Wei Song 0002, Jim D. Garside, Javier Navaridas, Zhiying Wang. 9-16 [doi]
- GALS Partitioning by Behavioural Decoupling Expressed in Petri NetsDanil Sokolov, Alex Yakovlev. 17-26 [doi]
- Modelling Mixed 4phase Pipelines: Structures and PatternsGraham M. Birtwistle, Kenneth S. Stevens. 27-36 [doi]
- Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked SystemsJoycee Mekie. 37-44 [doi]
- Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous RoutersEvangelia Kasapaki, Jens Sparsø. 45-52 [doi]
- Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans. 53-60 [doi]
- Synthesis of QDI FSMs from Synchronous SpecificationsFu-Chiung Cheng, Yuan-Feng Chen, Shu-Chuan Huang, Ching-Yang Huang. 61-68 [doi]
- Integrated Fanout Optimization and Slack Matching of Asynchronous CircuitsMehrdad Najibi, Peter A. Beerel. 69-76 [doi]
- Reconditioning: Automatic Power Optimization of QDI CircuitsArash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel. 77-84 [doi]
- Low Power Asynchronous VLSI with NEM RelaysBenjamin Z. Tang, Sunil A. Bhave, Rajit Manohar. 85-92 [doi]
- A New CMOS Topology for Low-Voltage Null Convention Logic Gates DesignMatheus Trevisan Moreira, Michel Evandro Arendt, Ricardo Aquino Guazzelli, Ney Laert Vilar Calazans. 93-100 [doi]
- Metastability in Better-Than-Worst-Case DesignsSalomon Beer, Marco Cannizzaro, Jordi Cortadella, Ran Ginosar, Luciano Lavagno. 101-102 [doi]
- A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous DesignMike Davies, Andrew Lines, Jon Dama, Alain Gravel, Robert Southworth, Georgios D. Dimou, Peter A. Beerel. 103-104 [doi]
- Test and Repair Flow for Shared BISR in Asynchronous Multi-processorsGang Wang, Xu Wang, Xinke Chen, Shuangbai Xue. 105-107 [doi]
- Clockless Design Performance Monitoring for Nanometer TechnologiesMarc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels. 108-109 [doi]
- Performance and Area Optimization of a Bundled-Data Intel Processor through ResynthesisArash Saifhashemi, Dylan Hand, Peter A. Beerel, William Koven, Hong Wang. 110-111 [doi]