Abstract is missing.
- A Pausible Bisynchronous FIFO for GALS SystemsBen Keller, Matthew Fojtik, Brucek Khailany. 1-8 [doi]
- How to Synchronize a Pausible Clock to a ReferenceRobert Najvirt, Andreas Steininger. 9-16 [doi]
- A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed PipelineL. C. Trudeau, Ghyslain Gagnon, François Gagnon, Claude Thibeault, T. Awad, D. Morrissey. 17-18 [doi]
- Synchronizers and Data Flip-Flops are DifferentJerome Cox, George Engel, David M. Zar, Ian W. Jones. 19-20 [doi]
- Blade - A Timing Violation Resilient Asynchronous TemplateDylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel. 21-28 [doi]
- Design and Verification of Speed-Independent Multiphase Buck ControllerDanil Sokolov, Victor Khomenko, Andrey Mokhov, Alex Yakovlev, David Lloyd. 29-36 [doi]
- DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOSSean Keller, Alain J. Martin, Chris Moore. 37-44 [doi]
- Timing Driven Placement for Quasi Delay-Insensitive CircuitsRobert Karmazin, Stephen Longfield Jr., Carlos Tadeo Ortega Otero, Rajit Manohar. 45-52 [doi]
- Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian RelaxationGang Wu, Ankur Sharma, Chris C. N. Chu. 53-60 [doi]
- Performance Optimization and Analysis of Blade Designs under Delay VariabilityDylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel. 61-68 [doi]
- Analyzing Isochronic Forks with Potential CausalityRajit Manohar, Yoram Moses. 69-76 [doi]
- Naturalized Communication and TestingMarly Roncken, Swetha Mettala Gilla, Hoon Park, Navaneeth Jamadagni, Chris Cowan, Ivan Sutherland. 77-84 [doi]
- AES Hardware-Software Co-design in WSNCarlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar. 85-92 [doi]
- Low Power Monolithic 3D IC Design of Asynchronous AES CoreNeela Lohith Penmetsa, Christos Sotiriou, Sung Kyu Lim. 93-99 [doi]
- Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient FaultsGuangda Zhang, Jim D. Garside, Wei Song 0002, Javier Navaridas, Zhiying Wang. 100-107 [doi]
- Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous ArbitersGabriele Miorandi, Davide Bertozzi, Steven M. Nowick. 108-115 [doi]
- Opportunistic Merge ElementAndrey Mokhov, Victor Khomenko, Danil Sokolov, Alex Yakovlev. 116-123 [doi]
- Design and Analysis of Testable Mutual Exclusion ElementsYang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin Breuer, Ney Laert Vilar Calazans, Peter A. Beerel. 124-131 [doi]
- Asynchronous Charge Sharing Power Consistent Montgomery MultiplierJiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana. 132-138 [doi]
- Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic TechnologyEldar Zianbetov, Edith Beigné, Gregory di Pendina. 139-146 [doi]