Abstract is missing.
- Opportunistic Mutual ExclusionKarthi Srinivasan, Yoram Moses, Rajit Manohar. 1-9 [doi]
- An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic ComputingPrafull Purohit, Johannes Leugering, Rajit Manohar. 1-10 [doi]
- Timed Signalling ProcessesRajit Manohar, Yoram Moses. 10-19 [doi]
- Case Study for Skewing MTNCL CircuitsCole Sherrill, Kyle Orman, Nicholas Brown, Jia Di. 20-26 [doi]
- Designing Self-timed Asynchronous Circuits with ChiselJilin Zhang, Chunqi Qian, Dexuan Huo, Jian Zhang, Hong Chen 0002. 27-33 [doi]
- Yak: An Asynchronous Bundled Data Pipeline Description LanguageCarsten Nielsen, Zhe Su, Giacomo Indiveri. 34-41 [doi]
- A 28nm Energy-efficient Asynchronous SNN Accelerator with On-chip Learning for Gas RecognitionDexuan Huo, Jilin Zhang, Jian Zhang, Hong Chen 0002. 42-47 [doi]
- ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive LogicZaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer. 48-57 [doi]
- A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell LibrariesMatheus Trevisan Moreira, William Koven, Tony F. Wu, H. Ekin Sumbul, Edith Beigné. 58-59 [doi]
- Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis AlgorithmsMackenzie J. Wibbels, Baudouin Chauviere, Kenneth S. Stevens. 60-70 [doi]
- A Novel Asynchronous Network-On-Chip Based on Source Asynchronous SignalingVenkata Nori, Baudouin Chauviere, Mackenzie J. Wibbels, Kenneth S. Stevens. 71-77 [doi]
- Verification-Driven Design for Asynchronous VLSIXiang Wu, Rajit Manohar. 78-88 [doi]
- Core Interface Optimization for Multi-core Neuromorphic ProcessorsZhe Su, Hyunjung Hwang, Tristan Torchet, Giacomo Indiveri. 89-98 [doi]
- Flexible Compilation and Refinement of Asynchronous CircuitsEbelechukwu Esimai, Marly Roncken. 109-119 [doi]