Abstract is missing.
- An Asynchronous RISC-V-based SNN Processor with Custom ISA Extensions for Programmable On-Chip LearningXuanyu Zhang, Jilin Zhang, Haoyang Huang, Hong Chen 0002. 1-8 [doi]
- Scaledmatx One : A Bundled-Data GALS Inference ASICJon Dama. 9-12 [doi]
- Mount Sisyphus: Energy-Efficient Asynchronous RISC-V Microcontroller in Intel 3 ProcessAndrew Lines, Ruokun Liu. 13-18 [doi]
- Efficient FPGA Implementation of Time-Domain Popcount for Low-Complexity Machine LearningShengyu Duan, Marcos L. L. Sartori, Rishad A. Shafik, Alex Yakovlev, Emre Ozer. 19-27 [doi]
- A Synthesis Toolflow for the Predictable Implementation of High-Performance Bundled-Data Asynchronous NoCs on FPGAGiuseppe Chessa, Elena Bellodi, Michele Favalli, Davide Zoni, Davide Bertozzi. 28-37 [doi]
- Distributed Locally Synchronous Grid Oscillator via Perpetual Token ExchangeJosef Salzmann. 38-45 [doi]
- Clock Generator with Clock Domain CrossingRobert Karmazin, Andrew Lines, Prasad Joshi, Benjamin Hill 0001. 46-55 [doi]
- Muller C-Element for NEMSPhilipp Lehninger, Axel Jantsch, Andreas Steininger, Elliott Worsey, Victor Marot, Dinesh Pamunuwa. 56-62 [doi]
- *Danil Sokolov, Victor Khomenko, Marco Sautto. 63-64 [doi]
- Synthesis and Timing Constraints for Reliable MTNCL Asynchronous CircuitsCole Sherrill, Ethan Brugger, Jia Di. 65-73 [doi]
- Innovations in MTNCL Gate Design: An Alternative MTCMOS Power-Gating ApproachCole Sherrill, Kile Harvey, Zhihan Weng, Jia Di. 74-79 [doi]
- Translating General Slack Elastic Programs into Dataflow CircuitsXiayuan Wen, Rui Li, Rajit Manohar. 80-88 [doi]
- Asynchronous Design of a Bitwise Elimination Argmax via High-Level Modeling in GraphRackHugh Squires-Parkin, Alex Chan, Rishad A. Shafik, Adrian Wheeldon, Alex Yakovlev. 89-98 [doi]
- Automated Decomposition of Concurrent Programs for Asynchronous Logic SynthesisKarthi Srinivasan, Rajit Manohar. 99-107 [doi]
- Hierarchical Event Readout with Asynchronous Pipelined Opportunistic MergesLeo Liu, Kwabena Boahen 0001. 108-117 [doi]
- Asynchronous, event-driven readout for large-scale imaging devicesPrafull Purohit, Rajit Manohar. 118-125 [doi]
- Post-Placement Timing Optimisations on Asynchronous DesignsDimitrios Tsalapatas, Nikolaos Chatzivangelis, Christos P. Sotiriou, Nikolaos Sketopoulos. 126-134 [doi]
- Timing Closure in Relative Timed Asynchronous Designs using Deep Reinforcement LearningSumanth Kolluru, Kenneth S. Stevens. 135-141 [doi]
- Investigating the Effects of Permanent Faults in QDI Circuits: A Formal PerspectiveRaghda El Shehaby, Matthias Függer, Florian Huemer, Andreas Steininger. 142-150 [doi]