Yifei Zhang. Design of Low-Floor Quasi-Cyclic IRA Codes and Their FPGA Decoders. PhD thesis, University of Arizona, Tucson, USA, 2007. [doi]
@phdthesis{basesearch-1505,
title = {Design of Low-Floor Quasi-Cyclic IRA Codes and Their FPGA Decoders},
author = {Yifei Zhang},
year = {2007},
url = {https://www.base-search.net/Record/9b24cf16ccf84f9db842efb9103adbef37dcfbcd9f40b0bd8fb77d5cfe138753},
note = {base-search.net (ftunivarizona:oai:arizona.openrepository.com:10150/195295)},
researchr = {https://researchr.org/publication/basesearch-1505},
cites = {0},
citedby = {0},
school = {University of Arizona, Tucson, USA},
}