Robert J. Halstead. Using Multithreaded Techniques to Mask Memory Latency on FPGA Accelerators. PhD thesis, University of California, Riverside, USA, 2015. [doi]
@phdthesis{basesearch-5496,
title = {Using Multithreaded Techniques to Mask Memory Latency on FPGA Accelerators},
author = {Robert J. Halstead},
year = {2015},
url = {https://www.base-search.net/Record/583dc66f53ff252a5bcf54719d294e8b53eefc3c49040b4c7d11bf37a92a8fe1},
note = {base-search.net (ftcdlib:qt45m0d5b0)},
researchr = {https://researchr.org/publication/basesearch-5496},
cites = {0},
citedby = {0},
school = {University of California, Riverside, USA},
}