Abstract is missing.
- Writing and verifying a Quantum optimizing compiler (keynote)Robert Rand 0001. 1 [doi]
- QSSA: an SSA-based IR for Quantum computingAnurudh Peduri, Siddharth Bhat, Tobias Grosser. 2-14 [doi]
- QRANE: lifting QASM programs to an affine IRBlake Gerard, Tobias Grosser, Martin Kong. 15-28 [doi]
- A polynomial time exact solution to the bit-aware register binding problemMichael Canesche, Ricardo S. Ferreira, José Augusto Miranda Nacif, Fernando Magno Quintão Pereira. 29-40 [doi]
- Graph transformations for register-pressure-aware instruction schedulingGhassan Shobaki, Justin Bassett, Mark Heffernan, Austin Kerbow. 41-53 [doi]
- Caviar: an e-graph based TRS for automatic code optimizationSmail Kourta, Adel Abderahmane Namani, Fatima Benbouzid-Si Tayeb, Kim M. Hazelwood, Chris Cummins, Hugh Leather, Riyadh Baghdadi. 54-64 [doi]
- On the computation of interprocedural weak control closureAbu Naser Masud, Björn Lisper. 65-76 [doi]
- Seamless deductive inference via macrosArash Sahebolamri, Thomas Gilray, Kristopher K. Micinski. 77-88 [doi]
- One-shot tuner for deep learning compilersJaehun Ryu, Eunhyeok Park, Hyojin Sung. 89-103 [doi]
- Training of deep learning pipelines on memory-constrained GPUs via segmented fused-tiled executionYufan Xu, Saurabh Raje, Atanas Rountev, Gerald Sabin, Aravind Sukumaran-Rajam, P. Sadayappan. 104-116 [doi]
- MLIR-based code generation for GPU tensor coresNavdeep Katel, Vivek Khandelwal, Uday Bondhugula. 117-128 [doi]
- Automating reinforcement learning architecture design for code optimizationHuanting Wang, Zhanyong Tang, Cheng Zhang, Jiaqi Zhao, Chris Cummins, Hugh Leather, Zheng Wang 0001. 129-143 [doi]
- Memory access scheduling to reduce thread migrationsSana Damani, Prithayan Barua, Vivek Sarkar. 144-155 [doi]
- Performant portable OpenMPGuray Ozen, Michael Wolfe. 156-168 [doi]
- BinPointer: towards precise, sound, and scalable binary-level pointer analysisSun Hyoung Kim, Dongrui Zeng, Cong Sun 0001, Gang Tan. 169-180 [doi]
- Cape: compiler-aided program transformation for HTM-based cache side-channel defenseRui Zhang, Michael D. Bond, Yinqian Zhang. 181-193 [doi]
- Making no-fuss compiler fuzzing effectiveAlex Groce, Rijnard van Tonder, Goutamkumar Tulajappa Kalburgi, Claire Le Goues. 194-204 [doi]
- Loner: utilizing the CPU vector datapath to process scalar integer dataArmand Behroozi, Sunghyun Park 0004, Scott A. Mahlke. 205-217 [doi]
- Mapping parallelism in a functional IR through constraint satisfaction: a case study on convolution for mobile GPUsNaums Mogers, Lu Li, Valentin Radu, Christophe Dubach. 218-230 [doi]
- Software pre-execution for irregular memory accesses in the HBM eraSanyam Mehta, Gary Elsesser, Terry Greyzck. 231-242 [doi]
- Efficient profile-guided size optimization for native mobile applicationsKyungwoo Lee, Ellis Hoag, Nikolai Tillmann. 243-253 [doi]