Table of Contents

• Architecturally Aligned Trustworthy AI: Substrate and System Design Strategies for Next Generation AI: KeynoteEren Kurshan. 1-8 [doi]
• Bridging the gap between software and hardwareLana Josipovic. 9 [doi]
• StAccato: Reducing the Performance Penalty of RandomnessRanganath Selagamsetty, Joshua San Miguel, Mikko H. Lipasti. 10-19 [doi]
• FlIP: Flow-Based Instruction Processing for Out-of-Order Scheduling in GPGPUsMunawira Kotyad, Yashvardhan Rathore, Ganesh Sai Shanmukhi, Virendra Singh. 20-28 [doi]
• LightSerial: Accelerating In-Process Isolation via Implicit Dependency ExposureYue Jin, Yibin Xu, Han Wang, Tianyue Lu, Mingyu Chen 0001. 29-38 [doi]
• Implications of Supporting Compressed Instructions in Area-Optimized Bit-Serial RISC-V CoresMeinhard Kissich, Daniel Traussnig, Marcel Baunach. 39-48 [doi]
• An Open-Source Distributed Simulation Framework for RISC-V Systems incorporating Vector and Cryptographic ExtensionsNikolaos Tampouratzis, Ioannis Papaefstathiou. 49-57 [doi]
• Accuracy-Performance-Resources Trade-Offs in RISC-V Microarchitectures for Genetic ProgrammingPaul Allaire, Mickaël Dardaillon, Thibaut Marty, Alfonso Rodríguez 0002, Andrés Otero, Karol Desnos. 58-66 [doi]
• Robust Quantum Communication for Space Systems Through an Heterogeneous RISC-V based FPGA/SoC PlatformGiorgio Cora, Arash Amini Bardpareh, Gonzalo Miguel Joaquin Fernandez Lobo, Corrado De Sio, Sarah Azimi, Andrea Stanco, Luca Sterpone. 67-70 [doi]
• Threads or Vectors? Evaluating SPMD and Vector Accelerators for Resource Constrained RISC-V ArchitecturesAmirhossein Kiamarzi, Samuele Colmi, Yvan Tortorella, Angelo Garofalo, Davide Rossi 0001, Giuseppe Tagliavini. 71-79 [doi]
• SMX: A RISC-V ISA Extension for Scale-Adaptive Quantized SoftmaxLuca Donato, Tommaso Spagnolo, Cristina Silvano. 80-89 [doi]
• How Much Energy Is Wasted in LLM operations? Evidence from Kernel-Level DVFSJeffrey Spaan, Kuan-Hsun Chen, Ana Lucia Varbanescu. 90-100 [doi]
• Compact Thermal and Power Models for Manycore Multichiplet Architectures: A Case Study on Intel Sapphire Rapids ProcessorAntonio del Vecchio, Giacomo Madella, Roberto Diversi, Andrea Bartolini. 101-108 [doi]
• SeT-Diff: Towards Semantic Foundation Models for HPC Telemetry and Time-SeriesGiovanni B. Esposito, Francesco Antici, Daniele Cesarini, Andrea Bartolini. 109-112 [doi]
• M3SA: Exploring Datacenter Performance and Climate-Impact with Multi- and Meta-Model Simulation and AnalysisRadu Nicolae, Dante Niewenhuis, Sacheendra Talluri, Alexandru Iosup. 113-117 [doi]
• Simulating MPI Collectives on Tofino Smart Switches in SimGridAhmad Moh'd Saleh A. Belbeisi, Majid Salimi Beni, Thomas Erbesdobler, Ehab Saleh, Matthew Tovey, Amir Raoofy, Josef Weidendorfer. 118-121 [doi]
• NoCWalk: In-Network Page Walks for Efficient Pointer-Chasing Workloads on MulticoresYuan Yao 0009, Shiming Li, Rashid Aligholipour, Stefanos Kaxiras. 122-132 [doi]
• A QSP Matrix Multiplication Method for Phase Factor RecoveryZheng Zhang, Minzhong Luo. 133-139 [doi]
• D3OF: DRL-Driven Dual-Layer Dynamic Obfuscation Framework for FPGAsFei Cao, Weiping Yao, Chaobing Wang. 140-148 [doi]
• Efficient and Accurate Graph Classification with Hyperdimensional Computing on FPGAJebacyril Arockiaraj, Dhruv Parikh, Viktor Prasanna 0001. 149-159 [doi]
• LSFAF: A Layer-Sharing and FPGA-Accelerated Framework for Fast Collaborative Inference in Edge ScenariosBin Zheng, Yujie Peng, Zhenkai Sun, Jianxin Wang, Jin Wang. 160-168 [doi]
• Network Folding for Resource-Efficient Implementation of Stream-Dataflow Deep Neural Network Inference on FPGAsVan-Quan Pham, Adrien Prost-Boucle, Olivier Muller, Frédéric Pétrot. 169-178 [doi]
• AExec: Asynchronous Multi-accelerator Execution and Management MechanismXiaokun Pei, Zhuolun Jiang, Mingyu Chen, Songyue Wang, Tianyue Lu. 179-187 [doi]
• SABRE: A Compression-Aware BF16 Accelerator for Neuromorphic AttentionKunal Kishore, Manish Nagaraju, Anshul Raghavendra Katti, Nandan Venkataramana Bhat, Pramod Udupa, Shikha Tripathi, TSB Sudarshan. 188-196 [doi]
• A 8.4 TFLOPS@16b/4.3W General-Purpose Programmable Accelerated Cluster for AI-Native RANMarco Bertuletti, Yichao Zhang 0003, Alessandro Vanelli-Coralli, Luca Benini. 197-200 [doi]
• HMix : An Efficient Hardware Accelerator for Quantized MLP-Mixer InferenceDhananjay Rao Thallikar Shyam, Shashank Nag, Lizy K. John. 201-209 [doi]
• A System-Level Performance Analysis of On-Device Learning on an Ultra-Low-Power Edge SystemManuele Rusci, Mohamed Amine Hamdi, Daniele Jahier Pagliari, Francesco Conti 0001, Alessio Burrello. 210-213 [doi]
• Ada-Store: An Adaptive Load-aware Hybrid Storage Architecture for Bursty WorkloadsLuyang Ni, Jiexiong Xu, Yiquan Chen, Yijing Wang, Wenzhi Chen. 214-221 [doi]
• Hardware-Constrained Online Coordination for Hybrid CXL-RDMA Disaggregated MemoryYue Ma, Ying Jing, Peng He, Fangming Liu, Sheng Zhang. 222-231 [doi]
• AME-PIM: Can Memory be Your Next Tensor Accelerator?Emanuele Venieri, Simone Manoni, Alberto Florian, Jaehyun Park, Kyomin Sohn, Andrea Bartolini. 232-240 [doi]
• Strata: Proactive Page Placement in Hybrid Memory SystemsUpasna, Venkata Kalyan Tavva. 241-244 [doi]
• Topology and Reliability Aware Qubit Mapping for Quantum Core SystemsRajeswari Suance P. S, Akansh Khandelwal, Surankan De, Satyajit Das, John Jose, Maurizio Palesi. 245-253 [doi]
• Quantum Walks for Collision-Based Information Set DecodingSimone Perriello, Alessandro Barenghi, Gerardo Pelosi. 254-262 [doi]
• Similarity-Aware Function Pre-Loading for Serverless InferenceJichang Dong, Bao Li 0002, Yusong Tan. 263-266 [doi]
• PrudentCaster: A Tunable Broadcast Gossip Framework for Mobile Edge SynchronizationYunna Cui, Liwei Shen, Mingming Hu, Boxiong Zhang, Tieying Li. 267-270 [doi]
• A Portable GPU Kernel Performance Modeling Method Based on LLVM IR Dynamic Feature PredictionQiang Wang 0062, Hao Zheng 0004, Yiru Liu, Fan Yang, Jiachen Liu, Chaojun Deng, Ziheng Wang 0002, Xiaoshe Dong. 271-279 [doi]
• MKA: Memory-Keyed Attention for Efficient Long-Context ReasoningDong Liu, Yanxuan Yu, Ben Lengerich, Ying Nian Wu. 280-289 [doi]
• Row-wise Inter-Phase Pipelining for Hardware-Efficient GCN AccelerationShi Chen, Junsheng Chang, Yang Guo 0003, Li Shen 0007. 290-298 [doi]
• EnsembleHealer: Autonomous Recovery from Model Poisoning in Decentralized Federated LearningSrinija Ramichetty, Mahmoud Abumandour, Alaa R. Alameldeen, Guru Venkataramani. 299-308 [doi]
• On the Efficacy of PyTorch for High-Performance Computing: A Case Study in Computational PhysicsBeau Johnston, Niteya Shah, Wu-chun Feng. 309-317 [doi]
• Parameter-Efficient and Imbalance-Aware Fine-Tuning for Rhetorical Role Classification in Legal JudgmentsPavithra Neelamegam, S. Jaya Nirmala. 318-322 [doi]
• LLM-Driven Optimization for High-Level SynthesisMax Ramstad, Nicolas Bohm Agostini, Antonino Tumeo. 323-326 [doi]
• wdCP: Windowed Incremental Checkpointing for Efficient and Bounded LLM RecoveryWendi Cheng, Xiao Zhang 0014, Xiaonan Zhao, Xiaoling Shu, Jinjiang Wang, Shujie Han 0001. 327-330 [doi]
• POSTER: A Reliable Multi-FPGA RISC-V Based Cluster for Space AI InferenceGiorgio Cora, Morgana Duni, Corrado De Sio, Sarah Azimi, Luca Sterpone. 331-332 [doi]
• POSTER: A Chip-level Monitoring Framework for Enhancing PCIe ObservabilityHaobin Zheng. 333-334 [doi]
• POSTER: AI Act Sandboxes: A Safety-by-Co-Design FrameworkNadia Spatari. 335-336 [doi]
• POSTER: Bypassing Blocking Instructions to enable Out-Of-Order Execution in GPGPUsMunawira Kotyad, Ganesh Sai Shanmukhi, Yashvardhan Rathore, Virendra Singh. 337-338 [doi]
• POSTER: TinyLLM: Evaluation and Optimization of Small Language Models for Agentic Tasks on Edge DevicesMohd Ariful Haque, Fahad Rahman, Kishor Datta Gupta, Khalil Shujaee, Roy George. 339-340 [doi]
• POSTER: Security and Cost Trade-offs of Side-Channel Countermeasures for AES Software on RISC-V SoCsAbolfazl Sajadi, Nusa Zidaric, Todor Stefanov, Nele Mentens. 341-342 [doi]
• POSTER: Toward Energy-Efficient Approximate Computing for Mixture-of-Experts Based CNN InferenceJob van wee, Yawar Rasheed, G. A. Gillani. 343-344 [doi]
• POSTER: Measuring What Matters: Advancing Green Computing Through the Green Work Efficiency (GWE) MetricMirna Elbestar, Mariam Dawoud, Soumaia Al Ayyat, Sara Singergy, Sherif G. Aly 0001. 345-346 [doi]
• POSTER: Hardware Acceleration for Graph Neural NetworksCory Davis, Patrick M. Stockton, Eugene B. John, Jeeho Ryoo, Ebod Shojaei. 347-348 [doi]
• POSTER: Enabling Fine-Grain DVFS for Multi-Kernel GPU WorkloadsJeffrey Spaan, Kuan-Hsun Chen, Ana Lucia Varbanescu. 349-350 [doi]
• POSTER: Reinforcement Learning-based QoS-aware Online Scheduling for Multi-Tenant DNN Inference on Heterogeneous AcceleratorsFrancesco Giulio Blanco, Enrico Russo 0002, Maurizio Palesi, Davide Patti. 351-352 [doi]
• POSTER: Towards a RISC-V-based SmartNIC Architecture on FPGAKun Qin, Aswathy Nedumpalli Sankaranarayanan, Taiki Okano, Martin Schulz 0001, Carsten Trinitis. 353-354 [doi]