Abstract is missing.
- A Real-Time and Energy-Efficient 3D Gaussian Splatting-based Geometric and Semantic Mapping Processor with 2-level Redundancy Handling for Embodied AgentsSeryeong Kim, Jongjun Park, Hyungnam Joo, Sangmyoung Lee, Wonhoon Park, Seokchan Song, Junha Ryu, Gwangtae Park, Sangjin Kim, Jiwon Choi, Seongyon Hong, Wooyoung Jo, Hyeonrae Kim, Hoi-Jun Yoo. 1-3 [doi]
- Multicore Encryption-Decryption Hardware Accelerator for Torus-Based RLWE FHEInfall Syafalni, Najmi Az-Zahra Feryputri, Nana Sutisna, Nur Ahmadi, Rahmat Mulyawan, Tutun Juhana, Trio Adiono. 1-3 [doi]
- Key Profiling-Driven Heuristic Machine Learning Predictor for Mapping Strategy Selection in Heterogeneous Multi-Core NUMA SystemsYifan Jin, Sichen Tao, Mulya Agung, Masatoshi Kawai, Hiroyuki Takizawa. 1-6 [doi]
- PRAVE: Partial Out-of-Order Execution for Superscalar Processors with Vector ExtensionMasayuki Kimura, Ryota Shioya. 1-6 [doi]
- CFX: A Conflict-Free and Exponent-Scaled FFT/IFFT Accelerator on FPGA SoC for Energy-Efficient Edge ComputingRyo Maeda, Thi Hong Tran, Vu Trung Duong Le, Anh Kiet Pham, Van Tinh Nguyen, Yasuhiko Nakashima. 1-6 [doi]
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT SecurityAnh Kiet Pham, Van Truong Vo, Vu Trung Duong Le, Tuan Hai Vu 0001, Hoai Luan Pham, Van Tinh Nguyen, Yasuhiko Nakashima. 1-6 [doi]
- RX VPU: A High-Efficiency Variable-Length Vector Architecture with Widening Reduction MAC for Embedded CNNsRyosuke Higashi, Takeshi Nitta, Akaru Oishi, Kiwamu Takada, Yasuhiro Sugita, Yoichi Yuyama, Hidekazu Bingo, Boyu Tseng, Sugako Otani, Hiroyuki Kondo. 1-6 [doi]
- Low-Power and High-Input-Impedance Buffer Circuit for EEG Acquisition Using a Self-Cascode StructureMasayuki Fujita, Daisuke Kanemoto, Tetsuya Hirose. 1-5 [doi]
- Neuromorphic Hardware Acceleration of Multiplication with 16 nm FinFETsLogan Larsh, Jonas D. Manchester, Jonathan Jones, Sarah Sharif, Yaser Mike Banad. 1-3 [doi]
- A cyclic pipeline ADC for light and rainfall detection sensorsYing Li, Wenyuan Li. 1-6 [doi]
- Strategic Job Deferral: Turning Process Variations into Power SavingsPeng He, Yuan He 0002, Yuyang Liu, Yasutaka Wada. 1-6 [doi]
- Evaluating a Programmable DNN Accelerator for On-Chip Bragg Peak Localization in X-ray Detector ASICs: A Case Study and Performance EvaluationHoku Ishibe, Connor Bohannon, Yukinori Sato, Kazutomo Yoshii. 1-6 [doi]
- COOL-Splat: A HW/SW Co-optimized Online 3D Gaussian Splatting Modeling Accelerator for Energy-Efficient 3D Modeling on Mobile DevicesJongjun Park, Seryeong Kim, Seokchan Song, Wonhoon Park, Junha Ryu, Jiwon Choi, Hoi-Jun Yoo. 1-3 [doi]
- PACOX: A FPGA-based Pauli Composer Accelerator for Pauli String ComputationTran Xuan Hieu Le, Tuan Hai Vu 0001, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima. 1-6 [doi]
- Spikceiver: Compact Audio-Visual Spiking Transformer with Depthwise Splitting and Bottleneck AttentionJiajun Zhong, Vu Trung Duong Le, Hoai Luan Pham, Yasuhiko Nakashima. 1-6 [doi]
- MicroXPU: An Energy-Efficient Low-bit LLM Accelerator with Microscaling Format-Tailored Digital Compute-in-Memory MacroJiwon Choi, Seongyon Hong, Wooyoung Jo, Wonhoon Park, Sunjoo Whang, Seryeong Kim, Jongjun Park, Sangjin Kim, Hoi-Jun Yoo. 1-3 [doi]