Table of Contents

• Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal AcquisitionAlba Páez-Montoro, Javier De Mena Pacheco, Marisa López-Vallejo, Celia López-Ongil, Susana Patón. 1-6 [doi]
• High-Rate Acquisition System for an Infrared LPSMiguel Cubero, David Moltó, Elena Aparicio-Esteve, Álvaro Hernández, José Manuel Villadangos, Jesús Ureña. 1-6 [doi]
• ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication TransceiversPedro Barba, Alberto Rodríguez-Pérez, Enrique Prefasi, Rocío Del Río, Oscar Guerra. 1-5 [doi]
• Low-power EEGNet-based Brain-Computer Interface implemented on an Arduino Nano 33 SenseDaniel Enériz, Nicolás Medrano, Belén Calvo, Diego Antolín. 1-5 [doi]
• GBW Optimization in Two-Stage OTAs Operating in Weak InversionJavier Beloso-Legarra, Antonio Lopez-Martin, Carlos Aristoteles De la Cruz, Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi. 1-4 [doi]
• Implementing a CNN in FPGA Programmable Logic for NILM ApplicationMiguel Tapiador, Laura de Diego-Otón, Álvaro Hernández, Rubén Nieto. 1-6 [doi]
• Time-Sensitive Networking to meet Hard-real Time Boundaries on Edge Intelligence ApplicationsArmando Astarloa, Pedro Fernández, Jesús Lázaro 0001, Mikel Idirin, Sergio Salas. 1-6 [doi]
• Real-time iris image quality evaluation implemented in Ultrascale MPSoCCamilo A. Ruiz-Beltrán, Adrián Romero-Garcés, M. González, J. A. Rodríguez, Antonio Bandera, Antonio Sánchez-Pedraza. 1-6 [doi]
• SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of AstrophysicsSelenia María Medina Hernández, Pedro P. Carballo, Pedro Hernández-Fernández, David S. Miranda Guillén, Sergio González. 1-6 [doi]
• Design Space Analysis for a Digital Lock-In Amplifier for Infrared Gas Sensor Signal AcquisitionAlberto Ramírez-Bárcenas, Mario García-Valderas, Celia López-Ongil. 1-6 [doi]
• Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI TechnologyMax Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González 0004, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Josep Oltra, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Hugo Safadi, Víctor Soria 0001, Alejandro Suanes, Iván Vargas, Fernando Arreza, Roger Figueras, Pau Fontova-Musté, Joan Marimon, Ricardo Martínez, Sergio Moreno, Jordi Sacristán, Oscar Alonso, Xavier Aragonès, Adrián Cristal, Ángel Diéguez, Manuel López, Diego Mateo, Francesc Moll, Miquel Moretó, Oscar Palomar, Marco A. Ramírez, Francesc Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa. 1-6 [doi]
• Any-Radix Efficient Fully-Parallel Implementation of the Fast Fourier Transform on FPGAsIgnacio Amat Hernández, Juan A. López. 1-6 [doi]
• Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source toolsJosé-Miguel Galeas-Merchán, José-Borja Castillo-Sánchez, Martín González-García. 1-6 [doi]
• Flexible Deep-pipelined FPGA-based Accelerator for Spiking Neural NetworksSamuel López Asunción, Pablo Ituero Herrero. 1-6 [doi]
• Definition of a SoC Architecture for a High-Rate Correlator BankDavid Moltó, Miguel Cubero, Elena Aparicio-Esteve, Álvaro Hernández, Jose M. Villadangos, Jesús Ureña. 1-6 [doi]
• SoC Architecture for Acquisition and Processing of EMG SignalsVíctor M. Navarro, Rubén Nieto, Pedro R. Fernández, Álvaro Hernández, Antonio J. del Ama, Susana Borromeo. 1-6 [doi]
• CMOS Transistor Array for Cryogenic Temperature Characterization of MOS ComponentsJorge Pérez-Bailón, Santiago Celma, Carlos Sánchez-Azqueta. 1-5 [doi]
• Approximate arithmetic aware training for stochastic computing neural networksChristiam F. Frasser, Alejandro Morán, Vincent Canals, Joan Font, Eugeni Isern 0001, Miquel Roca 0001, Josep L. Rosselló. 1-6 [doi]
• Accelerators in Embedded Systems for Machine Learning: A RISCV ViewAlejandra Sanchez-Flores, Lluc Alvarez, Bartomeu Alorda-Ladaria. 1-6 [doi]
• Making Digital N-Path MixersHasan Moussa, Jessica Gonsalves, Estelle Lauga-Larroze, Sana Ibrahim, Florence Podevin, Sylvain Bourdel, Laurent Fesquet. 1-5 [doi]
• An ultra-low power custom IoT node for gas sensing applicationsJuan Luis Soler-Fernández, Omar Romera, Ángel Diéguez, Joan Daniel Prades, Oscar Alonso. 1-6 [doi]
• High-Throughput DTW accelerator with minimum area in AMD FPGA by HLSMarco Hormigo-Jiménez, Javier Hormigo. 1-6 [doi]
• HW/SW implementation of RSA digital signature on a RISC-V-based System-on-ChipApurba Karmakar, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Piedad Brox. 1-6 [doi]
• A Simple Power Analysis of an FPGA implementation of a polynomial multiplier for the NTRU cryptosystemEros Camacho-Ruiz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Erica Tena-Sánchez, Piedad Brox. 1-6 [doi]
• Integrated Cuk Inverter for Single-Phase Grid-Tied Photovoltaic SystemAnderson Aparecido Dionizio, Leonardo Poltronieri Sampaio, Sérgio Augusto Oliveira da Silva. 1-6 [doi]
• Devices and circuits for HF applications based on 2D materialsSimon Skrzypczak, Di Zhou, Wei Wei, Dalal Fadil, Dominique Vignaud, Emiliano Pallecchi, Henri Happy. 1-5 [doi]
• Study of foveation mechanisms in Dynamic Vision SensorsIsabel Ortíz-Ramírez, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona. 1-6 [doi]
• Comparative Analysis of Neural Network Implementations for NILM ApplicationsJorge Martín, Laura de Diego, Miguel Tapiador, Álvaro Hernández, Rubén Nieto. 1-6 [doi]
• Ethernet Emulation over PCIe for RISC-V Software Development VehiclesDavid Castells-Rufas, Xavier Martorell, Aleix Roca, Alexander Kropotov, Xavier Teruel, Teresa Cervero, John D. Davis. 1-6 [doi]
• A 5.2-GS/s 8-Parallel 1024-Point MDC FFTPedro Paz, Mario Garrido. 1-6 [doi]
• A Compact Double-Exponential Circuit for Single Event Transient EmulationSebastià A. Bota, Salvador Barcelo, Gabriel Torrens, Rafel Perelló, Jaume Verd, Ivan de Paúl, Jaume Segura 0001. 1-6 [doi]
• Three-Stage Low Dropout Regulator with Enhanced Transient Response and Regulation PerformanceAndrés Fernando Serrano Reyes, María Teresa Sanz-Pascual, Belén Calvo López, Nicolás Medrano. 1-5 [doi]
• RISC-V for Genome Data Analysis: Opportunities and ChallengesLorién López-Villellas, Esteve Pineda-Sánchez, Asaf Badouh, Santiago Marco-Sola, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó. 1-6 [doi]
• Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installationsGabriel Santana Quintana, Pedro P. Carballo, Carlos Betancor. 1-6 [doi]
• Design of GFET-based active modulators leveraging device performance reproducibility conditionsAnibal Pacheco-Sanchez, Javier Noé Ramos-Silva, Nikolaos Mavredakis, Eloy Ramírez-García, David Jiménez. 1-6 [doi]
• UML-Based Design Flow for Systems with Neural NetworksDaniel Suárez, Héctor Posadas, Víctor Fernández 0001. 1-6 [doi]
• Automatic code generation from UML for data memory optimization in microcontrollersHéctor Posadas, José Luis Vázquez, Eugenio Villar. 1-6 [doi]
• Stochastic Computing-based on-chip Training Circuitry for Reservoir Computing SystemsFabio Galán-Prado, Joan Font-Rosselló, Miquel Roca 0001, Josep L. Rosselló. 1-6 [doi]
• A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacksVirginia Zúñiga-González, Erica Tena-Sánchez, Antonio J. Acosta. 1-6 [doi]
• Timing requirements on multi-processing and reconfigurable embedded systems with multiple environmentsSara Alonso, Jesús Lázaro 0001, Jaime Jiménez, Leire Muguira, Unai Bidarte. 1-6 [doi]
• Using Current to Drive Two SDC Memristors Connected in Series and in Anti-SeriesAlbert Cirera, Pere Lluís Miribel-Català, Antonio Rubio 0001, Blas Garrido, Jordi Colomer-Farrarons, Ioannis Vourkas. 1-5 [doi]
• Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network AcceleratorsRoland Müller, Loreto Mateu, Ralf Brederlow. 1-6 [doi]
• High Resolution Current Measurement Using TMR SensorsNicolás Medrano, Diego Antolín, Daniel Enériz, Belén Calvo. 1-5 [doi]
• An Automatic Generator of Non-Power-of-Two SDF FFT Architectures for 5G and BeyondVíctor Manuel Bautista, Mario Garrido. 1-6 [doi]
• SET and SEU Hardened Clock Gating CellMarko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Milos Krstic. 1-6 [doi]
• A Two-Stage Amplifier in a Low Power 32.768 kHz Quartz Crystal OscillatorMarine Brun, Gilles Jacquemod, Yoann Charlon, Arnaud Gamet, Philippe Le Fevre. 1-6 [doi]
• An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture ExplorationRafael Tornero, David Rodriguez, José Maria Martínez, José Flich. 1-6 [doi]