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Peter-Michael Seidel. On the design of IEEE compliant floating point units and their quantitative analysis. PhD thesis, Saarland University, Saarbrücken, Germany, 1999. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: On the design of IEEE compliant floating-point units and their quantitative analysisPeter-Michael Seidel. PhD thesis, Saarland University, 2007. [doi] Design of an On-Line IEEE Floating-Point Addition Unit for FPGAsSteven D. Krueger, Peter-Michael Seidel. fccm 2004: 239-246 [doi]
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