Analysis and architectural support for parallel stateful packet processing

Javier VerdĂș. Analysis and architectural support for parallel stateful packet processing. PhD thesis, Polytechnic University of Catalonia, Spain, 2008. [doi]

@phdthesis{es-2056,
  title = {Analysis and architectural support for parallel stateful packet processing},
  author = {Javier VerdĂș},
  year = {2008},
  url = {http://hdl.handle.net/10803/6027},
  researchr = {https://researchr.org/publication/es-2056},
  cites = {0},
  citedby = {0},
  school = {Polytechnic University of Catalonia, Spain},
}