Abstract is missing.
- Separation Logic-Assisted Code Transformations for Efficient High-Level SynthesisFelix Winterstein, Samuel Bayliss, George A. Constantinides. 1-8 [doi]
- A Fully Pipelined and Dynamically Composable Architecture of CGRAJason Cong, Hui Huang 0001, Chiyuan Ma, Bingjun Xiao, Peipei Zhou. 9-16 [doi]
- Reducing Processing Latency with a Heterogeneous FPGA-Processor FrameworkJonathon Pendlum, Miriam Leeser, Kaushik Chowdhury. 17-20 [doi]
- Integrated CUDA-to-FPGA Synthesis with Network-on-ChipSwathi T. Gurumani, Jacob Tolar, Yao Chen, Yun Liang, Kyle Rupnow, Deming Chen. 21-24 [doi]
- GraphGen: An FPGA Framework for Vertex-Centric Graph ComputationEriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, Jose F. Martinez, Carlos Guestrin. 25-28 [doi]
- Using Multi-op Instructions as a Way to Generate ASIPs with Optimized Pipeline StructureYosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv. 29 [doi]
- FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable RegionsChristophe Huriaux, Olivier Sentieys, Russell Tessier. 30 [doi]
- Customizable Compression Architecture for Efficient Configuration in CGRAsSyed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen. 31 [doi]
- Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable ArchitecturesDajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei. 32 [doi]
- Mapping Tasks to a Dynamically Reconfigurable Coarse Grained ArrayMansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan. 33 [doi]
- Better-Than-DMR Techniques for Yield ImprovementShunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima. 34 [doi]
- A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES ArchitectureTian Xiang, Lei Zhao, Xi Jin, Tianqi Wang, Shaoping Chu, Cong Ma, Shubin Liu, Qi An, Xue Ben. 35 [doi]
- A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector MultiplicationJeremy Fowers, Kalin Ovtcharov, Karin Strauss, Eric S. Chung, Greg Stitt. 36-43 [doi]
- A New Algorithm for Carry-Free Addition of Binary Signed-Digit NumbersKlaus Schneider 0001, Adrian Willenbücher. 44-51 [doi]
- On Hard Adders and Carry Chains in FPGAsJason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz. 52-59 [doi]
- Breaking Sequential Dependencies in FPGA-Based Sparse LU FactorizationSiddhartha, Nachiket Kapre. 60-63 [doi]
- An Efficient Architecture for Floating-Point Eigenvalue DecompositionXinying Wang, Joseph Zambreno. 64-67 [doi]
- 3D FFTs on a Single FPGABenjamin Humphries, Hansen Zhang, Jiayi Sheng, Raphael Landaverde, Martin C. Herbordt. 68-71 [doi]
- Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAsBrad L. Hutchings, Jared Keeley. 72-79 [doi]
- System-Level Retiming and PipeliningGirish Venkataramani, Yongfeng Gu. 80-87 [doi]
- GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing ExtractionBenjamin Gojman, André DeHon. 88-95 [doi]
- Timing Fault Detection in FPGA-Based CircuitsEdward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre. 96-99 [doi]
- Design Space Exploration to Accelerate Nelder-Mead Algorithm Using FPGAPham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung. 100 [doi]
- Experiments in Mapping Expressions to DSP BlocksBajaj Ronak, Suhaib A. Fahmy. 101 [doi]
- Memory Optimized Re-gridding for Non-uniform Fast Fourier Transform on FPGAsUmer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar. 102 [doi]
- Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial ReconfigurationJames J. Davis, Peter Y. K. Cheung. 103 [doi]
- Accelerator of Stacked Convolutional Independent Subspace Analysis for Deep Learning-Based Action RecognitionLu He, Yan Luo, Yu Cao. 104 [doi]
- Building Optimized Packet Filters with COFFiSven Hager, Frank Winkler, Björn Scheuermann, Klaus Reinhardt. 105 [doi]
- From GPU to FPGA: A Pipelined Hierarchical Approach to Fast and Memory-Efficient NDN Name LookupYanbiao Li, Dafang Zhang, Xian Yu, Jing Long, Wei Liang. 106 [doi]
- High-Throughput Fixed-Point Object Detection on FPGAsXiaoyin Ma, Walid Najjar, Amit Roy-Chowdhury. 107 [doi]
- UTOPIA: Generic User-Level Access to the Physical Memory Address Space for IP Core Debugging and Validation on FPGA Based PCIe Extension CardsHendrik Noll, Sebastian Siegert, Johannes Hiltscher, Wolfgang Rehm. 108 [doi]
- FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStackStuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow. 109-116 [doi]
- LEAP Shared Memories: Automating the Construction of FPGA Coherent MemoriesHsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer. 117-124 [doi]
- Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and CustomQingshan Tang, Matthieu Tuna, Habib Mehrez. 125-132 [doi]
- Fast, Power-Efficient Biophotonic Simulations for Cancer Treatment Using FPGAsJeffrey Cassidy, Lothar Lilge, Vaughn Betz. 133-140 [doi]
- SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo ApplicationsThomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk. 141-148 [doi]
- FPGA Gaussian Random Number Generators with Guaranteed Statistical AccuracyDavid B. Thomas. 149-156 [doi]
- FPGA Implementation of EM Algorithm for 3D CT ReconstructionYoung Kyu Choi, Jason Cong, Di Wu. 157-160 [doi]
- A Scalable Multi-engine Xpress9 Compressor with Asynchronous Data TransferJoo-Young Kim, Scott Hauck, Doug Burger. 161-164 [doi]
- FPGA Accelerated Online Boosting for Multi-target TrackingMatthew Jacobsen, Pingfan Meng, Siddarth Sampangi, Ryan Kastner. 165-168 [doi]
- An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor DesignKaveh Aasaraai, Andreas Moshovos. 169 [doi]
- Abstract: Shared L2 Cache Management in Multicore Real-Time SystemGang Chen, Biao Hu, Kai Huang, Alois Knoll, Kai Huang, Di Liu. 170 [doi]
- Harmonica: An FPGA-Based Data Parallel Soft CoreChad D. Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, Hyesoon Kim. 171 [doi]
- FPGA Acceleration for Simultaneous Medical Image Reconstruction and SegmentationPeng Li, Thomas Page, Guojie Luo, Wentai Zhang, Pei Wang, Peng Zhang, Peter Maass, Ming Jiang, Jason Cong. 172 [doi]
- A Hierarchical Memory Architecture with NoC Support for MPSoC on FPGAsShiming Li, Miaoqing Huang, Hongyuan Ding, Sen Ma. 173 [doi]
- Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem SolverShuo Li, Ahmed Hemani. 174 [doi]
- FPGA Implementation of Optical Flow Algorithm Based on Cost AggregationYu Tanabe, Tsutomu Maruyama. 175 [doi]
- Image Signal Processors on FPGAsDi Wu, Andreas Moshovos. 176 [doi]
- A Fully-Pipelined FPGA Design for Tree-Reweighted Message Passing AlgorithmWenlai Zhao, Haohuan Fu, Guangwen Yang. 177 [doi]
- Speeding Up FPGA Placement: Parallel Algorithms and MethodsMatthew An, J. Gregory Steffan, Vaughn Betz. 178-185 [doi]
- Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear ProgrammingMarco Rabozzi, John Lillis, Marco D. Santambrogio. 186-193 [doi]
- A Grammar Induction Method for Clustering of Operations in Complex FPGA DesignsMuhsen Owaida, Christos D. Antonopoulos, Nikolaos Bellas. 194-201 [doi]
- Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for ZynqKizheppatt Vipin, Suhaib A. Fahmy. 202-205 [doi]
- MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow ComputationsDeheng Ye, Nachiket Kapre. 206-209 [doi]
- Automating Optimization of Reconfigurable DesignsMaciej Kurek, Tobias Becker, Thomas C. P. Chau, Wayne Luk. 210-213 [doi]
- Kung Fu Data Energy - Minimizing Communication Energy in FPGA ComputationsEdin Kadric, Kunal Mahajan, André DeHon. 214-221 [doi]
- Reconstructing AES Key Schedules from Decayed Memory with FPGAsHeinrich Riebler, Tobias Kenter, Christian Plessl, Christoph Sorge. 222-229 [doi]
- Low Power Reconfigurable Controllers for Wireless Sensor Network NodesVivek D. Tovinakere, Olivier Sentieys, Steven Derrien, Christophe Huriaux. 230-233 [doi]
- Compiling Higher Order Functional Programs to Composable Digital HardwareEduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides. 234 [doi]
- Fast Design-Space Exploration Method for SW/HW Codesign on FPGAsYuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada. 235 [doi]
- Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD SystemsSaad Arrabi, D. Moore, L. Wang, Kevin Skadron, Benton H. Calhoun, John Lach, Brett H. Meyer. 236 [doi]
- Fast and Power Efficient Heapsort IP for Image Compression ApplicationYuhui Bai, Syed Zahid Ahmed, Bertrand Granado. 237 [doi]
- A Hardware MPI Spawn for Distributed Multiprocessing Reconfigurable System on Chip (MP-RSoC)Roland Christian Gamom Ngounou Ewo, Andréa Pinna, Bertrand Granado, Martin Mbouenda, Hilaire Bertrand Fotsin. 238 [doi]
- MRAPI Implementation for Heterogeneous Reconfigurable Systems-on-ChipLaurent Gantel, Mohamed El Amine Benkhelifa, François Verdier, Fabrice Lemonnier. 239 [doi]
- Scheduling Mixed-Architecture Processes in Tightly Coupled FPGA-CPU Reconfigurable ComputersBrandon Kyle Hamilton, Michael Inggs, Hayden Kwok-Hay So. 240 [doi]
- A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD ResolutionHamed Tabkhi, Majid Sabbagh, Gunar Schirner. 241 [doi]
- High-Throughput and Low-Cost Hardware Accelerator for Privacy Preserving PublishingFumito Yamaguchi, Hiroaki Nishi. 242 [doi]
- Energy Reduction through Differential Reliability and Lightweight CheckingEdin Kadric, Kunal Mahajan, André DeHon. 243-250 [doi]
- A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle SensorRobért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener. 251-258 [doi]
- Look-up Table Design for Deep Sub-threshold through Full-Supply OperationMonther Abusultan, Sunil P. Khatri. 259-266 [doi]