Abstract is missing.
- Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGATimothy Sherwood. 1 [doi]
- CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and BeyondAlireza Khataei, Kia Bazargan. 2-11 [doi]
- Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s EthernetGreg Stitt, Wesley Piard, Christopher Crary. 12-21 [doi]
- MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAsShaoxian Xu, Sitong Lu, Zhiyuan Shao, Xiaofei Liao, Hai Jin 0001. 22-32 [doi]
- Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication EngineAndy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao. 33-39 [doi]
- DynaRapid: From C to FPGA in a Few SecondsAndrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne. 40 [doi]
- Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process TheoryHui Wei 0001, Jingyong Ye, Yutong Chen, Heng Wu. 40 [doi]
- Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust DesignAndy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao. 41 [doi]
- XUNI: Virtual Machine Abstraction for Self-contained and Multi-tenant Cloud FPGAsZelin Wang, Guiyuan Zhu, Yunhai Liu, Yisong Chang, Ke Zhang 0017, Mingyu Chen 0001. 41 [doi]
- ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGAMuhammed Kawser Ahmed, Christophe Bobda. 42 [doi]
- Accelerating Autonomous Path Planning on FPGAs with Sparsity-Aware HW/SW Co-OptimizationsXiaoyu Niu, Yanjun Zhang, Yifan Zhang, Hongzheng Tian, Bo Yu, Shaoshan Liu, Sitao Huang. 42 [doi]
- Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert ChannelsHassan Nassar, Philipp Machauer, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel. 43 [doi]
- FPGA-Placement via Quantum AnnealingThore Gerlach, Stefan Knipp, David Biesner, Stelios Emmanouilidis, Klaus Hauber, Nico Piatkowski. 43 [doi]
- Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow CircuitsAyatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne. 44-54 [doi]
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer AccelerationJinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi 0001, Peipei Zhou 0001. 55-66 [doi]
- LevelST: Stream-based Accelerator for Sparse Triangular SolverZifan He, Linghao Song, Robert F. Lucas, Jason Cong. 67-77 [doi]
- A 475 MHz Manycore FPGA Accelerator for RTL SimulationSahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus. 78-84 [doi]
- From Topology to Realization in FPGA/VPR RoutingMahdi Abbaszadeh, Dana L. How. 85-96 [doi]
- Formal Verification of Source-to-Source Transformations for HLSLouis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez 0001, Zhiru Zhang. 97-107 [doi]
- REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA DesignsDongjoon Park, André DeHon. 108-118 [doi]
- An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated CircuitsZhenyu Xu, Miaoxiang Yu, Jillian Cai, Saddam Gafsi, Judson Douglas Ryckman, Qing Yang 0001, Tao Wei. 119-129 [doi]
- SuperNIC: An FPGA-Based, Cloud-Oriented SmartNICWill Lin, Yizhou Shan, Ryan Kosta, Arvind Krishnamurthy, Yiying Zhang 0005. 130-141 [doi]
- My Fifteen Year Journey of Deploying FPGA Accelerated SolutionsPrabhat K. Gupta. 142 [doi]
- GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection NetworkChunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang 0012. 143-153 [doi]
- HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAsManoj B. Rajashekar, Xingyu Tian, Zhenman Fang. 154-164 [doi]
- A Statically and Dynamically Scalable Soft GPGPUMartin Langhammer, George A. Constantinides. 165-175 [doi]
- Evaluating Versal AI Engines for Option Price Discovery in Market Risk AnalysisMark Klaisoongnoen, Nick Brown 0002, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus. 176-182 [doi]
- E4SA: An Ultra-Efficient Systolic Array Architecture for 4-Bit Convolutional Neural NetworksGeng Yang, Jie Lei 0001, Zhenman Fang, Jiaqing Zhang, Junrong Zhang, Weiying Xie, Yunsong Li. 183 [doi]
- A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on FPGAsYan Chen, Kiyofumi Tanaka. 183 [doi]
- Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation FunctionYiyue Jiang, Andrius Vaicaitis, John Dooley, Miriam Leeser. 184 [doi]
- Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming ApproachStéphane Pouget, Louis-Noël Pouchet, Jason Cong. 184 [doi]
- AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA AcceleratorKai Qian, Zheng Liu, Yinqiu Liu, Haodong Lu 0001, Zexu Zhang, Ruiqiu Chen, Kun Wang 0005. 185 [doi]
- A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMsHongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang. 185 [doi]
- Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level IRsRuifan Xu, Jin Luo, Yun Liang 0001. 186 [doi]
- HR-GCN: An Efficient GCN Accelerator for Heterogeneous Graph Data and R-GCN ModelShengjun Xu, Wenlu Peng, Wenjin Huang, Qi Liu, Yihua Huang 0005. 186 [doi]
- Cross-FPGA Power Estimation from High Level Synthesis via Transfer-LearningZhigang Wei, Aman Arora, Emily Shriver, Lizy Kurian John. 187 [doi]
- Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip NetworksQizhe Wu, Letian Zhao, Yuchen Gui, Huawen Liang, Xiaotian Wang, Xi Jin 0002. 187 [doi]
- Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy BalancingJiahui Xu, Lana Josipovic. 188-198 [doi]
- POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor ComputationsXiaochen Hao, Hongbo Rong, Mingzhe Zhang, Ce Sun, Hong H. Jiang, Yun Liang 0001. 199-210 [doi]
- Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and SynthesisYouwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang 0001. 211-222 [doi]
- FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAsShulin Zeng, Jun Liu, Guohao Dai, Xinhao Yang, Tianyu Fu 0004, Hongyi Wang, Wenheng Ma, Hanbo Sun, Shiyao Li, Zixiao Huang, Yadong Dai, Jintao Li, Zehao Wang, Ruoyu Zhang, Kairui Wen, Xuefei Ning, Yu Wang. 223-234 [doi]
- Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft LogicDaniel Gerlinghoff, Benjamin Chen Ming Choong, Rick Siow Mong Goh, Weng-Fai Wong, Tao Luo 0014. 235-245 [doi]
- A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGAYizhao Gao, Baoheng Zhang, Yuhao Ding, Hayden Kwok-Hay So. 246-257 [doi]