Abstract is missing.
- A novel architecture for a secure update of cryptographic engines on trusted platform moduleSunil Malipatlolla, Thomas Feller, Abdulhadi Shoufan, Tolga Arul, Sorin A. Huss. 1-6 [doi]
- Scrubbing-based SEU mitigation approach for Systems-on-Programmable-ChipsAitzan Sari, Mihalis Psarakis. 1-8 [doi]
- Accelerated FPGA architecture design: Capabilities and limitations of analytical modelsJoydip Das, Steven J. E. Wilton. 1-8 [doi]
- Design & development of soft-core processor based remote terminal units for nuclear reactorsAditya Gour, A. Santhana Raj, R. P. Behera, N. Murali, S. A. V. Satya Murty. 1-4 [doi]
- FPGA implementation of reconfigurable ADPLL network for distributed clock generationC. Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard. 1-4 [doi]
- Pipelined high precision beamforming delay calculator for ultrasound imagingZhanxiang Zhao, Xi Jin, Xin Zhang. 1-4 [doi]
- A scalable network port scan detection system on FPGATejasvi Anand, Yagnesh Waghela, Kuruvilla Varghese. 1-6 [doi]
- A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAsThomas Marconi, Tulika Mitra. 1-6 [doi]
- Accelerating on-line training of LS-SVM with run-time reconfigurationShaojun Wang, Yu Peng, Guangquan Zhao, Xiyuan Peng. 1-6 [doi]
- An analytical energy model to accelerate FPGA logic architecture investigationSenthilkumar Thoravi Rajavel, Ali Akoglu. 1-8 [doi]
- Objective-driven workload allocation in heterogeneous computing systemsQiang Liu, Wayne Luk. 1-4 [doi]
- Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertionAntoine Morvan, Steven Derrien, Patrice Quinton. 1-10 [doi]
- The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable acceleratorKazuei Hironaka, Nobuaki Ozaki, Hideharu Amano. 1-4 [doi]
- Automating formal verification of customized soft-processorsKong Woei Susanto, Wayne Luk. 1-8 [doi]
- Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis toolTassadaq Hussain, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé. 1-8 [doi]
- A scalable memory interface for multicore reconfigurable computing systemsPhilip Garcia, Katherine Compton. 1-8 [doi]
- Partially reconfigurable system-on-chips for adaptive fault toleranceShaon Yousuf, Adam Jacobs, Ann Gordon-Ross. 1-8 [doi]
- Exploring FPGA technology mapping for fracturable LUT minimizationDavid Dickin, Lesley Shannon. 1-8 [doi]
- A low power technology mapping method for Adaptive Logic ModuleWei Chen, Xiaolin Zhang, Takeshi Yoshimura, Yuichi Nakamura. 1-5 [doi]
- A novel architecture for a secure update of cryptographic engines on trusted platform moduleSunil Malipatlolla, Thomas Feller, Abdulhadi Shoufan, Tolga Arul, Sorin A. Huss. 1-6 [doi]
- Hydrate: Hybrid Reconfigurable Architecture ExpressionsChi Wai Yu, Fred Cox, Wayne Luk, Ray C. C. Cheung. 1-4 [doi]
- Spiking neural network-based auto-associative memory using FPGA interconnect delaysChong H. Ang, Craig T. Jin, Philip Heng Wai Leong, André van Schaik. 1-4 [doi]
- Floating-point mixed-radix FFT core generation for FPGA and comparison with GPU and CPUBo Duan, Wendi Wang, Xingjian Li, Chunming Zhang, Peiheng Zhang, Ninghui Sun. 1-6 [doi]
- Timing speculation in FPGAs: Probabilistic inference of data dependent failure ratesSumanta Chaudhuri, Justin S. Wong, Peter Y. K. Cheung. 1-8 [doi]
- A threat-based Connect6 implementation on FPGAKizheppatt Vipin, Suhaib A. Fahmy. 1-4 [doi]
- High speed low complexity FPGA-based FIR filters using pipelined adder graphsMartin Kumm, Peter Zipf. 1-4 [doi]
- An FPGA-based object detector with dynamic workload balancingChuan Cheng, Christos-Savvas Bouganis. 1-4 [doi]
- ReSim: A reusable library for RTL simulation of dynamic partial reconfigurationLingkan Gong, Oliver Diessel. 1-8 [doi]
- Reconfigurable acceleration and dynamic partial self-reconfiguration in general purpose computingIoannis Sourdis, Abhijit Nandy, Venkatasubramanian Viswanathan, Anthony Brandon, Dimitris Theodoropoulos, Georgi Gaydadjiev. 1-8 [doi]
- An FPGA Connect6 Solver with a two-stage pipelined evaluationTakahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe. 1-4 [doi]
- A unified emulation/simulation environment for reconfigurable system-on-chip developmentPeter Crosthwaite, John W. Williams, Peter Sutton. 1-8 [doi]
- VLIW-SCORE: Beyond C for sequential control of SPICE FPGA accelerationNachiket Kapre, André DeHon. 1-9 [doi]
- An analysis of ring oscillator PUF behavior on FPGAsSusana Eiroa, Iluminada Baturone. 1-4 [doi]
- Sharing FPUs in many-soft-coresDavid Castells-Rufas, Eduard Fernandez-Alonso, Jordi Carrabina, Jaume Joven. 1-6 [doi]
- Formulation-level design space exploration for partially reconfigurable FPGAsRohit Kumar, Ann Gordon-Ross. 1-6 [doi]
- Partial reconfiguration logic synthesis by temporal slicingSwamy D. Ponpandi, Akhilesh Tyagi. 1-6 [doi]
- Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurationsMasayuki Kimura, Kazuei Hironaka, Hideharu Amano. 1-8 [doi]
- Cool Mega-Array: A highly energy efficient reconfigurable acceleratorNobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo. 1-8 [doi]
- Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architecturesSyed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen. 1-6 [doi]
- Design methodology for analog circuit designs using proposed field programmable basic analog building blocksGarima Kapur, C. M. Markan. 1-4 [doi]
- An adaptive-method for velocity estimation using time-to-digital converterKhadgi Mitesh, Koul Majid, M. Manivannan. 1-4 [doi]
- Design methodology for FPGA implementation of lattice piecewise-affine functionsM. C. Martinez-Rodriguez, Iluminada Baturone, P. Brox. 1-4 [doi]
- Efficient key-dependent message authentication in reconfigurable hardwareJérémie Crenne, Pascal Cotret, Guy Gogniat, Russell Tessier, Jean-Philippe Diguet. 1-6 [doi]
- Variable and clause elimination in SAT problems using an FPGAMasayuki Suzuki, Tsutomu Maruyama. 1-8 [doi]
- An FPGA implementation of a threat-based strategy for Connect6Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich. 1-4 [doi]
- A framework for FPGA acceleration of large graph problems: Graphlet counting case studyBrahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj. 1-8 [doi]
- Operational mode exploration for reconfigurable systems with multiple applicationsStefan Wildermann, Felix Reimann, Jürgen Teich, Zoran Salcic. 1-8 [doi]
- FPGA power consumption measurements and estimations under different implementation parametersDimitrios Meidanis, Konstantinos Georgopoulos, Ioannis Papaefstathiou. 1-6 [doi]
- Efficient region allocation for adaptive partial reconfigurationKizheppatt Vipin, Suhaib A. Fahmy. 1-6 [doi]
- Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidatesRabia Shahid, Malik Umar Sharif, Marcin Rogawski, Kris Gaj. 1-9 [doi]
- A reconfigurable macro-pipelined systolic accelerator architectureWenqi Bao, Jiang Jiang, Yuzhuo Fu, Qing Sun. 1-6 [doi]
- A self-healing autonomous neural network hardware for trustworthy biomedical systemsZhanpeng Jin, Allen C. Cheng. 1-8 [doi]
- A framework for verifying functional correctness in Odin IIJoseph C. Libby, Ashley Furrow, Paddy O'Brien, Kenneth B. Kent. 1-6 [doi]
- Enabling high level design of adaptive systems with partial reconfigurationKizheppatt Vipin, Suhaib A. Fahmy. 1-4 [doi]
- Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable ArchitectureRatna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy. 1-5 [doi]
- Runtime stress-aware replica placement on reconfigurable devices under safety constraintsJosef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich. 1-6 [doi]
- Hardware module reuse and runtime assembly for dynamic management of reconfigurable resourcesAbelardo Jara-Berrocal, Ann Gordon-Ross. 1-6 [doi]
- 3D implication logic: Preliminary resultsGina Adam. 1-3 [doi]
- Investigation of NBTI and PBTI induced aging in different LUT implementationsSaman Kiamehr, Abdulazim Amouri, Mehdi Baradaran Tahoori. 1-8 [doi]
- Constant power reconfigurable computingAdrien Le Masle, Gary Chun Tak Chow, Wayne Luk. 1-8 [doi]
- Hardware-accelerated execution of Pi-calculus reconfiguration schedulesAndré Seffrin, Sorin A. Huss. 1-8 [doi]
- High level synthesis of stereo matching: Productivity, performance, and software constraintsKyle Rupnow, Yun Liang, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen. 1-8 [doi]
- SW and HW co-design of Connect6 accelerator with scalable streaming coresKentaro Sano. 1-4 [doi]
- Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithmKazuhiro Negi, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri. 1-8 [doi]
- Architecture and tools for programmable QCARajeswari Devadoss, Kolin Paul, M. Balakrishnan. 1-4 [doi]