Table of Contents

• PrefaceYun Liang, Hiroki Nakahara, Wei Zhang, Fubing Mao, Ray Cheung. [doi]
• LCAM: Low-Cost Approximate Multiplier Design on FPGAMingyu Shu, Qiang Liu. 1 [doi]
• Design Exploration of RISC-V Soft-Cores through Speculative High-Level SynthesisJean-Michel Gorius, Simon Rokicki, Steven Derrien. 1-6 [doi]
• Dual-Triangular QR Decomposition with Global Acceleration and Partially Q-Rotation SkippingRui Fang, Siyang Jiang, Hsi-Wen Chen, Wei Ding, Ming-Syan Chen. 1-4 [doi]
• Hypersort: High-performance Parallel Sorting on HBM-enabled FPGASoundarya Jayaraman, Bingyi Zhang, Viktor K. Prasanna. 1-11 [doi]
• FPGA Implementation of Low-Latency Recursive Median FilterBo Peng, Yuzhu Zhou, Qiang Li, Maosong Lin, Jiankui Weng, Qiang Zeng. 1-7 [doi]
• A Lane Detection Hardware Algorithm Based on Helmholtz Principle and Its Application to Unmanned Mobile VehiclesKatsuaki Kamimae, Shintaro Matsui, Yasutoshi Araki, Takehiro Miura, Keigo Motoyoshi, Keizo Yamashita, Haruto Ikehara, Takuho Kawazu, Huang Yuwei, Masahiro Nishimura, Shuto Abe, Kenyu Okino, Yuta Hashiguchi, Koki Fukuda, Kengo Yanagihara, Taito Manabe, Yuichiro Shibata. 1-4 [doi]
• Modeling FPGA-based Architectures for RoboticsAriel Podlubne, Diana Göhringer. 1-4 [doi]
• Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level SynthesisXuefei He, Jianyi Cheng, George A. Constantinides. 1-4 [doi]
• Accelerating Transformer Neural Networks on FPGAs for High Energy Physics ExperimentsFilip Wojcicki, Zhiqiang Que, Alexander D. Tapper, Wayne Luk. 1-8 [doi]
• P3Net: PointNet-based Path Planning on FPGAKeisuke Sugiura, Hiroki Matsutani. 1-9 [doi]
• An Agile Tile-based Platform for Adaptive Heterogeneous Many-Core SystemsAhmed Kamaleldin, Diana Göhringer. 1-4 [doi]
• Desgin and Implementation of ROS2-based Autonomous Tiny Robot Car with Integration of Multiple ROS2 FPGA NodesHayato Mori, Hayato Amano, Akinobu Mizutani, Eisuke Okazaki, Yuki Konno, Kohei Sada, Tomohiro Ono, Yuma Yoshimoto, Hakaru Tamukoh, Takeshi Ohkawa, Midori Sugaya. 1-4 [doi]
• $p$LPAQ: Accelerating LPAQ Compression on FPGADongdong Tang, Xuan Sun 0003, Nan Guan, Tei-Wei Kuo, Chun Jason Xue. 1-6 [doi]
• A Masked Pure-Hardware Implementation of Kyber Cryptographic AlgorithmTendayi Kamucheka, Alexander Nelson, David Andrews 0001, Miaoqing Huang. 1 [doi]
• EXPRESS: CNN EXecution Time PREdiction for DPU DeSign Space ExplorationShikha Goel, Rajesh Kedia, Rijurekha Sen, M. Balakrishnan. 1-2 [doi]
• An Energy-Efficient K-means Clustering FPGA Accelerator via Most-Significant Digit First ArithmeticSaeid Gorgin 0001, MohammadHosein Gholamrezaei, Danial Javaheri, Jeong-A Lee. 1-4 [doi]
• Autonomous driving system with feature extraction using a binarized autoencoderKota Hisafuru, Ryotaro Negishi, Soma Kawakami, Dai Sato, Kazuki Yamashita, Keisuke Fukada, Nozomu Togawa. 1-4 [doi]
• A Lightweight FPGA-based IDS-ECU Architecture for Automotive CANShashwat Khandelwal, Shanker Shreejith. 1-9 [doi]
• LearningGroup: A Real-Time Sparse Training on FPGA via Learnable Weight Grouping for Multi-Agent Reinforcement LearningJe Yang, Jaeuk Kim, Joo-Young Kim 0001. 1-9 [doi]
• byteman: A Bitstream Manipulation FrameworkKristiyan Manev, Joseph Powell, Kaspar Matas, Dirk Koch. 1-9 [doi]
• The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural NetworksIoanna Souvatzoglou, Dimitris Agiakatsikas, George Antonopoulos, Vasileios Vlagkoulis, Aitzan Sari, Athanasios Papadimitriou, Mihalis Psarakis. 1 [doi]
• FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-designNobuho Hashimoto, Shinya Takamaeda-Yamazaki. 1-9 [doi]
• HPIPE NX: Boosting CNN Inference Acceleration Performance with AI-Optimized FPGAsMarius Stan, Mathew Hall, Mohamed Ibrahim, Vaughn Betz. 1-9 [doi]
• A Highly Customizable and Efficient Hardware Implementation for Parallel Matrix InversionSultan Alqahtani, Yiqun Zhu, Qizhi Shi, Xiaolin Meng, Xinhua Wang 0001. 1-2 [doi]
• GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph ProcessingXu Zhang, Yisong Chang, Tianyue Lu, Ke Liu 0004, Ke Zhang 0017, Mingyu Chen 0001. 1-2 [doi]
• Implementation and Improvement of Autonomous Robot Car using SoC FPGA with DPUAkira Kojima. 1-4 [doi]
• Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and ChallengesEnsieh Aliagha, Diana Göhringer. 1-11 [doi]
• Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource UsageBoma A. Adhi, Carlos Cortes, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano. 1-4 [doi]
• Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure LearningRyota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase. 1 [doi]
• FPGA implementation of HDR synthesis processing with image compression techniquesMasahiro Nishimura, Yuta Imamura, Taito Manabe, Yuichiro Shibata. 1-2 [doi]
• Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUFHayden Cook, Jonathan Thompson, Zephram Tripp, Brad Hutchings, Jeffrey Goeders. 1-10 [doi]
• Boosting Domain-Specific Debug Through Inter-frame CompressionZakary Nafziger, Martin Chua, Daniel Holanda Noronha, Steven J. E. Wilton. 1-10 [doi]
• Message from the General Chair and Program Co-ChairsWei Zhang, Ray Cheung, Yun Liang, Hiroki Nakahara. 1 [doi]
• CAPI-Precis: Towards a Compute-Centric Interface for Coherent Shared Memory AcceleratorsAbdullah T. Mughrabi, Gregory T. Byrd. 1-9 [doi]
• Parallel CRC On An FPGA At Terabit SpeedsQianfeng Clark Shen, Juan Camilo Vega, Paul Chow. 1-6 [doi]
• Memory-efficient RMT Matching Optimization Based on MBitTreeZhongpei Liu, Gaofeng Lv, Jichang Wang, Xiangrui Yang. 1-9 [doi]
• Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse EngineeringReilly McKendrick, Corey Simpson, Brent Nelson, Jeffrey Goeders. 1-5 [doi]
• A Markovian Approach for Detecting Failures in the Xilinx SEM coreTrishna Rajkumar, Johnny Öberg. 1-4 [doi]
• Efficient Reinforcement Learning Framework for Automated Logic Synthesis ExplorationYu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang. 1-6 [doi]
• Application Specific Instruction-Set Processors for Machine Learning ApplicationsMuhammad Ali 0010, Diana Göhringer. 1-4 [doi]
• Quality & Generality: A Flexible FPGA Re-Clustering Technique to Improve Packing and PlacementMohamed A. Elgammal, Vaughn Betz. 1-2 [doi]
• FSLAM: an Efficient and Accurate SLAM Accelerator on SoC FPGAsVibhakar Vemulapati, Deming Chen. 1-9 [doi]
• Fast and Flexible FPGA Development using Hierarchical Partial ReconfigurationDongjoon Park, Yuanlong Xiao, André DeHon. 1-10 [doi]
• Hardware SAT Solver-based Area-efficient Accelerator for Autonomous DrivingYusuke Inuma, Yuko Hara-Azumi. 1-4 [doi]
• Using integer linear programming for correctly rounded multipartite architecturesOrégane Desrentes, Florent de Dinechin. 1-8 [doi]
• Bandwidth Efficient Homomorphic Encrypted Matrix Vector Multiplication Accelerator on FPGAYang Yang 0111, Sanmukh R. Kuppannagari, Rajgopal Kannan, Viktor K. Prasanna. 1-9 [doi]
• Acceleration of Fast Sample Entropy Towards Biomedical Applications on FPGAsChao Chen, Bruno da Silva 0001, Jianqing Li, Chengyu Liu 0001. 1-4 [doi]
• NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator ArchitectureYuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar 0001. 1 [doi]
• Hardware-Efficient FPGA-Based Approximate Multipliers for Error-Tolerant ComputingShangshang Yao, Liang Zhang. 1-8 [doi]
• ESSPER: Elastic and Scalable System for High-Performance Reconfigurable Computing with Software-bridged APIsKentaro Sano, Atsushi Koshiba, Takaaki Miyajima, Tomohiro Ueno. 1 [doi]
• ZHW: A Numerical CODEC for Big Data Scientific ComputationMichael Barrow, Zhuanhao Wu, Scott Lloyd, Maya B. Gokhale, Hiren D. Patel, Peter Lindstrom 0001. 1-9 [doi]
• Automated Generation and Orchestration of Stream Processing Pipelines on FPGAsKaspar Mätas, Kristiyan Manev, Joseph Powell, Dirk Koch. 1-10 [doi]
• Load-Store Queue Sizing for Efficient Dataflow CircuitsJiantao Liu, Carmine Rizzi, Lana Josipovic. 1-9 [doi]
• A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure InfrastructureYukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu. 1-6 [doi]
• Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN TrainingMariko Tatsumi, Silviu-Ioan Filip, Caroline White, Olivier Sentieys, Guy Lemieux. 1-9 [doi]
• SALIENT: Ultra-Fast FPGA-based Short Read AlignmentBehnam Khaleghi, Tianqi Zhang, Cameron Martino, George Armstrong, Ameen Akel, Ken Curewitz, Justin Eno, Sean Eilert, Rob Knight, Niema Moshiri, Tajana Rosing. 1-10 [doi]