Table of Contents

• HBMalloc: Dynamic Memory Management in High-Level Synthesis for FPGA HBMYiqing Mao, Yanxing Jin, Wai-Shing Luk, Lingli Wang. 1-2 [doi]
• Gradient-Aware Depth Sensitivity Scoring for Optimizing Neural Network Pruning: (PhD Forum Paper)Zongcheng Yue, Dongwei Yan, Longyu Ma, Chiu-Wing Sham. 1-4 [doi]
• Field-Programmable Dynamic Deep LearningStewart Denholm, Wayne Luk. 1-2 [doi]
• An MLIR-Based Compiler for Hardware Acceleration with Recursion Support: (PhD Forum Paper)Jiangnan Li, Zhengyi Zhang, Xuegong Zhou, Lingli Wang. 1-4 [doi]
• Optimizing DNN Accelerator Compression Using Tolerable Accuracy LossZhiqiang Que, Anyan Zhao, José Gabriel F. Coutinho, Ce Guo, Wayne Luk. 1-2 [doi]
• FLUD: A Scalable and Configurable Systolic Array Design for LU Decomposition on FPGAsXingyu Tian, Geng Yang, Zhenman Fang. 1-9 [doi]
• Memory-Efficient Sketch Acceleration for Handling Large Network Flows on FPGAsZhaoyang Han, Yicheng Qian, Michael Zink, Miriam Leeser. 1-9 [doi]
• Resource Dependency-Aware Scheduling for High-Level Synthesis with GNN and SDCAoxiang Qin, Minghua Shen, Nong Xiao 0001. 1-9 [doi]
• Increasing the Scalability of Graph Convolution for FPGA-Implemented Event-Based Vision: (PhD Forum Paper)Piotr Wzorek, Kamil Jeziorek, Tomasz Kryjak, Andréa Pinna 0001. 1-4 [doi]
• A Hardware-Friendly Rotation Convolution Neural Network and its FPGA Implementation for Remote Sensing Scene ClassificationXiang Li, Jingwei Zhang, Junhua Xiang, Yongming Wang, Peng Wang, Yanrong Wang, Feng Xu, Meng Zhang, An Jing. 1-2 [doi]
• Design Multi-Model Accelerators via Automatically Extracting Computational Graph SimilaritiesJunyi Zhu 0016, Boyan Han, Qingjie Lang, Dunbo Zhang, Ruoxi Wang, Li Shen 0007. 1-2 [doi]
• Swift: A Multi-FPGA Framework for Scaling Up Accelerated Graph AnalyticsOluwole Jaiyeoba, Abdullah T. Mughrabi, Morteza Baradaran, Beenish Gul, Kevin Skadron. 1-10 [doi]
• MPD - Multi-Project Die Sharing Enabled by an Embedded FPGADirk Koch, Myrtle Shah, Gavaskar Kanagara, Riadh Ben Abdelhamid, Nguyen-Dao. 1-9 [doi]
• Parallel FPGA Routing with On-The-Fly Net DecompositionFahrican Kosar, Mirjana Stojilovic, Vaughn Betz. 1-9 [doi]
• GraphNoC: Graph Neural Networks for Application-Specific FPGA NoC Performance PredictionGurshaant Malik, Nachiket Kapre. 1-9 [doi]
• FINN-T: Compiling Custom Dataflow Accelerators for Quantized TransformersChristoph Berganski, Felix Jentzsch, Marco Platzner, Max Kuhmichel, Heiner Giefers. 1-10 [doi]
• TMM-DSE: Topology-Aware MLP-Mixer for QoR Prediction in HLS Design Space ExplorationJingwei Zhang, Jiyuan Pu, Hu Chen, Xiang Li, Meng Zhang. 1-4 [doi]
• Hardware-Efficient Homogenized Key-Point Selection for Visual SLAMMiyuru Thathsara, Damith Anhettigama, Siew Kei Lam, Duvindu Piyasena. 1-2 [doi]
• Efficient Table-Lookup Inference of Binarized Convolutions with Kernel-Level Binding on FPGAYuntao Han, He Li, Qiang Liu. 1-2 [doi]
• A Regression-Based Approach Towards Estimating the Area, Delay and Leakage Power of Synthesizable FPGA TilesMousa Al-Qawasmi, Andy Gean Ye. 1-10 [doi]
• A Table Look-Up Based Quantum Simulation Accelerator on an FPGAHaruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi. 1-2 [doi]
• Multiqueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved ParallelismAlexandre Singer, Hang Yan 0014, Guozheng Zhang, Mark C. Jeffrey, Mirjana Stojilovic, Vaughn Betz. 1-9 [doi]
• Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAsMuhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, Jürgen Teich. 1-9 [doi]
• A Parallel-Trial Double-Update Annealing Processor for Enabling Highly-Effective Solution Search of Constrained Combinatorial Optimization ProblemsAkira Hyodo, Satoru Jimbo, Daiki Okonogi, Genta Inoue, Thiem Van Chu, Masato Motomura, Kazushi Kawamura. 1-9 [doi]
• Compass: A Collaborative HLS Design Space Exploration Framework via Graph Representation Learning and Ensemble Bayesian OptimizationHuizhen Kuang, Lingli Wang. 1-9 [doi]
• HEPPO: Hardware-Efficient Proximal Policy Optimization a Universal Pipelined Architecture for Generalized Advantage EstimationHazem Taha, Ameer M. S. Abdelhadi. 1-9 [doi]
• Efficient DSP Packing Method for Neural Network AcceleratorZenan Cui, Jingwei Zhang, Weijiang Tang, Hu Chen, Jiaqi Liu, Lizi Zhang, Meng Zhang. 1-4 [doi]
• FPGA Routing Optimization Based on Multi-Level MUX ArchitectureXizheng Li, Kaichuang Shi, Wai-Shing Luk, Hao Zhou, Lingli Wang. 1-8 [doi]
• TableCache: An Open-Source, Configurable, Last-Level Cache for FPGA SystemsChris Keilbart, Lesley Shannon. 1-10 [doi]
• Load Balanced Sparse Bundle Adjustment Accelerator for CNN-Based Visual-Inertial Odometry on FPGAYunfei Xiang, Jincheng Yu, Yuanfan Xu, Yu Hu, Kaiyuan Guo, Yuhan Dong, Yu Wang. 1-2 [doi]
• Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAsEhsan Kabir, M. D. Arafat Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews 0001, Miaoqing Huang. 1-2 [doi]
• Sensing Timing Margin Contingencies in the Programmable Fabric of FPGAsArun Iyer, Nishant Pawar, Dinesh Gaitonde, Nanditha Rao. 1-9 [doi]
• CGRA-HD: An Efficient Reconfigurable Accelerator for Hyperdimensional Computing: (PhD Forum Paper)Jiayin Qin, Yuan Dai, Lingli Wang. 1-4 [doi]
• Accelerating RavÆn for Real-Time Satellite Image Change DetectionHongda Zhou, Weilin Tao, Oliver Diessel, Cormac Purcell. 1-2 [doi]