Enhanced FPGA Architecture and CAD Flow for Efficient Runtime Hardware Reconfiguration. (Architecture FPGA ame'liore'e et flot de conception pour une reconfiguration mate'rielle en ligne efficace) - researchr publication

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Christophe Huriaux. Enhanced FPGA Architecture and CAD Flow for Efficient Runtime Hardware Reconfiguration. (Architecture FPGA ame'liore'e et flot de conception pour une reconfiguration mate'rielle en ligne efficace). PhD thesis, University of Rennes 1, France, 2015. [doi]

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