Abstract is missing.
- Enabling high-level parallel programming on multi-FPGA clustersJuan Miguel De Haro Ruiz, Carlos Ávarez Martínez, Daniel Jiménez-González, Xavier Martorell Bofill. 1-9 [doi]
- BraggHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental ScienceMaksim Levental, Arham Khan, Ryan Chard, Kazutomo Yoshii, Kyle Chard, Ian T. Foster. 10-17 [doi]
- High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of SharesGento Hiruma, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi. 18-26 [doi]
- Resource-Constraint Bayesian Optimization for Soft Processors on FPGAsCe Guo, Haoran Wu, Wayne Luk. 27-36 [doi]
- Embedded Security Accelerators within Network-on-Chip EnvironmentsJulian Haase, Nico Volkens, Diana Goehringer. 37-43 [doi]
- Soft GPGPU versus IP cores: Quantifying and Reducing the Performance GapMartin Langhammer, George A. Constantinides. 44-52 [doi]
- Accelerated Spiking Convolutional Neural Networks for Scalable Population GenomicsFederico Corradi, Zhanbo Shen, Hanqing Zhao, Nikolaos Alachiotis 0001. 53-62 [doi]
- A data compressor for FPGA-based state vector quantum simulatorsKaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi. 63-70 [doi]
- Learned Index Acceleration with FPGAs: A SMART ApproachGeetesh More, Suprio Ray, Kenneth B. Kent. 71-80 [doi]
- A Hardware Solver for Simultaneous Linear Equations with Multistage Interconnection NetworkRikuya Tomii, Tetsu Narumi. 81-89 [doi]
- LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA ArchitecturesRaveena Raikar, Dirk Stroobandt. 90-98 [doi]
- VIPER: A VTR Interface for Placement with Error ResilienceKate Thurmer, Vaughn Betz. 99-108 [doi]
- CAD Techniques for NoC-Connected Multi-CGRA SystemsHaoran Wei, Omkar Bhilare, Hamas Waqar, Jason Helge Anderson. 109-118 [doi]
- Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction IssuanceYuxi Tan, Masaru Nishimura, Riadh Ben Abdelhamid, Bingjie Guo, QiXiang Gao, Yoshiki Yamaguchi. 119-125 [doi]
- Implementation and analysis of custom instructions on RISC-V for Edge-AI applicationsAjay Kumar M, Vineet Kumar, Deepu John, Shreejith Shanker. 126-129 [doi]
- MLIR-Based Homomorphic Encryption Compiler for GPUAi Nozaki, Takuya Kojima, Hiroshi Nakamura, Hideki Takase. 130-132 [doi]
- Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware ArchitecturesElias Barbudo, Thierry Grandpierre, Eva Dokládalová. 133-134 [doi]
- An End-to-End Programming Model for AI Engine ArchitecturesMaksim Levental, Arham Khan, Ryan Chard, Kyle Chard, Stephen Neuendorffer, Ian T. Foster. 135-136 [doi]