Table of Contents

• ® IPU E2200: Second Generation Infrastructure Processing Unit (IPU)Pat Fleming, Chihjen Chang, Derek Collier, Anjali Singhai, Stephen Doyle, Eliel Louzoun, David Lee, Vetrivel Ayyavu, Sarig Livne, Robert Hathaway, Tony Hurson, Jackson Ellis, Tamar Bar-Kanarik, Jonathan Kenny, Cristine Dumitrescu, Yaron Wolberger. 1-16 [doi]
• ConnectX-8 SuperNICIdan Burstein. 1-21 [doi]
• Memory: Almost The Only Thing That Matters : A revolution in memory architecture for the data centerMark Kuemerle. 1-30 [doi]
• A UCIe Optical I/O Retimer Chiplet for AI Scale-upVladimir Stojanovic. 1-22 [doi]
• Specialized IC for World-Lock Rendering in Augmented and Mixed Reality DevicesOhad Meitav, Jay Tsao. 1-18 [doi]
• TM Generative AI Architecture Powering AMD Instinct M350 Series GPUs and PlatformsMichael Steffen, Michael Floyd. 1-37 [doi]
• UB-mesh: An New Interconnection Technology for Large AI SuperNodeHeng Liao. 1-13 [doi]
• FABRIC8LABS Electrochemical Additive Manufacturing ECAM Enabled Thermal Solutions for the Al Data CenterMichael Matthews, Ian Winfield, Joseph Madril, Douglas De Aquino Castro, Charles Biset. 1-15 [doi]
• A 4.69mW LLM Processor with Binary/Ternary Weights for Billion-Parameter Llama ModelSangyeob Kim, Jungwan Lee, Byeongju Kim, Hoi-Jun Yoo. 1-18 [doi]
• EveractiveSelf-Powered SoC with Energy Harvesting, Wakeup Receiver, and Energy-Aware SubsystemBenton H. Calhoun, David D. Wentzloff, Kuo-Ken Huang, Kyle Craig. 1-31 [doi]
• MEGA.mini: A NPU with Novel Heterogeneous AI Processing Architecture Balancing Efficiency, Performance, and Intelligence for the Era of Generative AIDonghyeon Han, Anantha P. Chandrakasan. 1 [doi]
• Co-Packaged Silicon Photonics Switches for Gigawatt AI FactoriesGilad Shainer. 1-24 [doi]
• IBM's Power11 ProcessorWilliam Starke. 1-29 [doi]
• Azure Secure Hardware Architecture : A Robust Security Foundation for Cloud WorkloadsBryan Kelly. 1-23 [doi]
• Cuzco: A High-Performance RISC-V RVA23 Compatible CPU IPTy Garibay, Shashank Nemawarkar. 1-21 [doi]
• High Density Si-IPD Technologies as Enabler for High-Performance and Low-Power Consumption Processor ChipsMohamed Mehdi Jatlaoui, Jean-Marc Yannou. 1 [doi]
• CORSAIR:An In-Memory Computing ChipletArchitecture for Inference-Time Compute AccelerationSudeep Bhoja. 1-37 [doi]
• ENABLING AI Infrastructure : Tomahawk Ultra - Ultra Low Latency, High Bandwidth Ethernet Switch for HPC & AI/ML applicationsMohan Kalkunte, Asad Khamisy. 1-22 [doi]
• Clo-HDnn: Continual On-Device Learning Accelerator with Hyperdimensional Computing via Progressive SearchChang Eun Song, Weihong Xu, Keming Fan, Soumil Jain, Gopabandhu Hota, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Gert Cauwenberghs, Tajana Rosing, Mingu Kang. 1-25 [doi]
• Adelia: A 4nm LLM Processor for Efficient Generative Al InferenceSeungjae Moon, Jung Hoon Kim, Juntaek Oh, Jay Kim, Joo-Young Kim 0001. 1 [doi]
• Up and Running with Rapidus : How Japan and Cutting-Edge Technologies are Transforming Semiconductor ManufacturingAtsuyoshi Koike. 1-49 [doi]
• Taping Out Three Class Chips Per Semester in Intel 16 TechnologyLucy Revina, Ethan Gao, Ken Ho, Daniel Lovell, Kristofer S. J. Pister, Borivoje Nikolic. 1-53 [doi]
• TM Pollara 400 AI NIC Architecture and ApplicationKevin Chu. 1-35 [doi]
• Bit-Separable Transformer Accelerator Leveraging Output Activation Sparsity for Efficient DRAM AccessSeunghyun Park, Daejin Park. 1-9 [doi]
• EdgeDiff: Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization for On-device Generative AI MotivationSangjin Kim, Jungjun Oh, Jeonggyu So, Yuseon Choi, Sangyeob Kim, Dongseo Kim, Gwangtae Park, Hoi-Jun Yoo. 1 [doi]
• ® Processor with Efficiency CoresDon Soltis, Stephen Robinson. 1-15 [doi]
• IRIS: A 8.55 mJ/frame Spatial Computing SoC for Real-time Interactable-Rendering and Surface-aware-Modeling with 3D Gaussian SplattingSeokchan Song, Seryeong Kim, Wonhoon Park, Jongjun Park, Sanghyuk An, Gwangtae Park, Minseo Kim, Hoi-Jun Yoo. 1 [doi]
• KLIMA: Low-latency mixed-signal In-Memory Computing accelerator for solving arbitrary-order Boolean SatisfiabilityTinish Bhattacharya, Dongseok Kwon, George Higgins Hutchinson, Xiangyi Zhang, Giacomo Pedretti, Fabian Böhm, John Paul Strachan, Thomas Van Vaerenbergh, Ray Beausoleil 0001, Ignacio Rozada, Dmitri B. Strukov. 1-7 [doi]
• Ironwood: Delivering Best in Class perf, perf/TCO and perf/Watt for Reasoning Model Training and ServingNorman P. Jouppi, Sridhar Lakshmanamurthy. 1-26 [doi]
• Passage M1000 : A 3D Photonic Interposer for AIDarius Bunandar. 1-34 [doi]
• PEZY-SC4s : The Fourth Generation MIMD Many-core Processor with High Energy Efficiency and Flexibility for HPC and AI ApplicationsNaoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Toru Koizumi 0001, Ryota Shioya, Kei Ishii. 1-42 [doi]
• Presto: A Unified RISC-V-Compatible SoC for Multi-Scheme FHE Acceleration over Module LatticeLuchang Lei, Yu Duan, Cheng Peng, Yongqing Zhu, Gangfeng Du, Zhenyu Guan, Huazhong Yang, Yongpan Liu, Zhen Gu, Song Bian 0001, Hongyang Jia. 1-40 [doi]
• Photonic Interconnect for Accelerated Computing Celestial AI Photonic Fabric Module - The world's first SoC with in-die Optical IOPhil Winterbottom. 1-13 [doi]
• BROCA: A Low-power and Low-latency Conversational Agent RISC-V System-on-Chip for Voice-interactive Mobile DevicesWooyoung Jo, Seongyon Hong, Jiwon Choi, Beomseok Kwon, Haoyang Sang, Dongseok Im, Sangyeob Kim, Sangjin Kim, Chaeyun Jeong, Yujin Moon, Hoi-Jun Yoo. 1 [doi]
• RTX 5090: Designed for the Age of Neural RenderingMarc Blackstein. 1-20 [doi]
• Basilisk: A 34mm² End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS : Integrated Systems Laboratory (ETH Zürich)Philippe Sauter, Thomas Benz, Paul Scheffler, Martin Poviser, Frank K. Gürkaynak, Luca Benini. 1-14 [doi]
• AMD RDNA 4 Radeon 9000 Series GPUAndy Pomianowski, Laks Pappu. 1-23 [doi]
• Hot ChipsKeynoteNoam Shazeer. 1-45 [doi]