Abstract is missing.
- ParaSplit: A Scalable Architecture on FPGA for Terabit Packet ClassificationJeffrey Fong, Xiang Wang, Yaxuan Qi, Jun Li 0003, Weirong Jiang. 1-8 [doi]
- A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT)John W. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, Tom English, Kees A. Vissers. 9-16 [doi]
- Rx Stack Accelerator for 10 GbE Integrated NICFrançois Abel, Christoph Hagleitner, Fabrice Verplanken. 17-24 [doi]
- Caliper: Precise and Responsive Traffic GeneratorMonia Ghobadi, Geoffrey Salmon, Yashar Ganjali, Martin Labrecque, J. Gregory Steffan. 25-32 [doi]
- Weighted Differential SchedulerHans Eberle, Wladek Olesinski. 33-39 [doi]
- Performance Evaluation of Open MPI on Cray XE/XK SystemsSamuel K. Gutierrez, Nathan T. Hjelm, Manjunath Gorentla Venkata, Richard L. Graham. 40-47 [doi]
- Performance Analysis and Evaluation of InfiniBand FDR and 40GigE RoCE on HPC and Cloud Computing SystemsJérôme Vienne, Jitong Chen, Md. Wasi-ur-Rahman, Nusrat S. Islam, Hari Subramoni, Dhabaleswar K. Panda. 48-55 [doi]
- Bufferless Routing in Optical Gaussian Macrochip InterconnectZhemin Zhang, Zhiyang Guo, Yuanyuan Yang. 56-63 [doi]
- Occupancy Sampling for Terabit CEE SwitchesFredy D. Neeser, Nikolaos Chrysos, Rolf Clauberg, Daniel Crisan, Mitchell Gusat, Cyriel Minkenberg, Kenneth M. Valk, Claude Basso. 64-71 [doi]