Abstract is missing.
- The Named-State Register File: Implementation and PerformancePeter R. Nuth, William J. Dally. 4-13
- Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar ProcessorsShlomo Weiss. 14-21
- Non-Consistent Dual Register Files to Reduce Register PressureJosep Llosa, Mateo Valero, Eduard Ayguadé. 22-31
- Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor SystemsChunming Qiao, Rami G. Melhem. 34-43
- Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection NetworkFranck Cappello, Cécile Germain. 44-53
- Abstracting Network Characteristics and Locality Properties of Parallel SystemsAnand Sivasubramaniam, Aman Singla, Umakishore Ramachandran, H. Venkateswaran. 54-63
- Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory MultiprocessorsFredrik Dahlgren, Per Stenström. 68-77
- How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?Keith I. Farkas, Norman P. Jouppi, Paul Chow. 78-89
- Creating a Wider Bus Using Caching TechniquesDaniel Citron, Larry Rudolph. 90-99
- Origin-Based Fault-Tolerant routing in the MeshRan Libeskind-Hadas, Eli Brandt. 102-111
- Efficient and Balanced Adaptive Routing in Two-Dimensional MeshesJatin Upadhyay, Vara Varavithya, Prasant Mohapatra. 112-121
- Fault-Tolerant Adaptive Routing for Two-Dimensional MeshesChris M. Cunningham, Dimiter R. Avresky. 122-131
- DASC CacheAndré Seznec. 134-143
- A Design Frame for Hybrid Access CachesKevin B. Theobald, Herbert H. J. Hum, Guang R. Gao. 144-153
- Software Assistance for Data CachesOlivier Temam, Nathalie Drach. 154-163
- Modeling Virtual Channel Flow Control in HypercubesYounes M. Boura, Chita R. Das. 166-175
- An Initial Evaluation of the Convex SPP-1000 for Earth and Space Science ApplicationThomas L. Sterling, Daniel Savarese, Phillip Merkey, Jeffrey P. Gardner. 176-185
- Simulation Study of Cached RAID5 DesignsKent Treiber, Jai Menon. 186-197
- Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel ProcessorsStuart Fiske, William J. Dally. 210-221
- Implementation of Atomic Primitives on Distributed Shared Memory MultiprocessorsMaged M. Michael, Michael L. Scott. 222-231
- Improving Performance by Cache Driven Memory ManagementKarl Westerholz, Stephen Honal, Josef Plankl, Christian Hafer. 234-242
- U-Cache: A Cost-Effective Solution to the Synonym ProblemJesung Kim, Sang Lyul Min, Sanghoon Jeon, Byoungchul Ahn, Deog Kyoon Jeong, Chong-Sang Kim. 243-252
- Access Ordering and Memory-Conscious Cache UtilizationSally A. McKee, William A. Wulf. 253-262
- An Argument for Simple COMAAshley Saulsbury, Tim Wilkinson, John B. Carter, Anders Landin. 276-285
- Software Cache Coherence for Large Scale MultiprocessorsLeonidas I. Kontothanassis, Michael L. Scott. 286-295
- Design and Performance Evaluation of a Multithreaded ArchitectureRamaswamy Govindarajan, Shashank S. Nemawarkar, Phillip LeNir. 298-307
- Fine-Grain Multi-Thread Processor Architecture for Massively Parallel ProcessingTetsuo Kawano, Shigeru Kusakabe, Rin-ichiro Taniguchi, Makoto Amamiya. 308-317
- A VLSI Architecture for Computer the Tree-to-Tree DistanceRaghu Sastry, N. Ranganathan. 330-339
- Massively Parallel Array Processor for Logic, Fault, and Design Error SimulationYoungmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang. 340-347
- Architectural Support for Inter-Stream Communication in a MSIMD SystemVivek Garg, David E. Schimmel. 348-357
- Optimizing Instruction Cache Performance for Operating System Intensive WorkloadsJosep Torrellas, Chun Xia, Russell L. Daigle. 360-369
- Program Balance and Its Impact on High Performance RISC ArchitecturesLizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor. 370-379