Abstract is missing.
- Stack Value File: Custom Microarchitecture for the StackHsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson. 5-14 [doi]
- Register Renaming and Scheduling for Dynamic Execution of Predicated CodePerry H. Wang, Hong Wang 0003, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen. 15-26 [doi]
- Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order ProcessorsPierre Michaud, André Seznec. 27-36 [doi]
- Speculative Data-Driven MultithreadingAmir Roth, Gurindar S. Sohi. 37 [doi]
- Towards Virtually-Addressed Memory HierarchiesXiaogang Qiu, Michel Dubois. 51-62 [doi]
- Reevaluating Online Superpage Promotion with Hardware SupportZhen Fang, Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sally A. McKee. 63-72 [doi]
- Performance of Hardware Compressed Main MemoryBülent Abali, Hubertus Franke, Xiaowei Shen, Dan E. Poff, T. Basil Smith. 73 [doi]
- JETTY: Filtering Snoops for Reduced Energy Consumption in SMP ServersAndreas Moshovos, Gokhan Memik, Babak Falsafi, Alok N. Choudhary. 85-96 [doi]
- A New Scalable Directory Architecture for Large-Scale MultiprocessorsManuel E. Acacio, José González, José M. García, José Duato. 97-106 [doi]
- Self-Tuned Congestion Control for Multiprocessor NetworksMithuna Thottethodi, Alvin R. Lebeck, Shubhendu S. Mukherjee. 107 [doi]
- Automatically Mapping Code on an Intelligent Memory ArchitectureJaejin Lee, Yan Solihin, Josep Torrellas. 121 [doi]
- CARS: A New Code Generation Framework for Clustered ILP ProcessorsKrishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala. 133 [doi]
- An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-CachesSe-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar. 147-158 [doi]
- DRAM Energy Management Using Software and Hardware Directed Power Mode ControlVictor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin. 159-170 [doi]
- Dynamic Thermal Management for High-Performance MicroprocessorsDavid Brooks, Margaret Martonosi. 171 [doi]
- Dynamic Prediction of Critical Path InstructionsEric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder. 185-196 [doi]
- Dynamic Branch Prediction with PerceptronsDaniel A. Jiménez, Calvin Lin. 197-206 [doi]
- Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage EfficiencyBart Goeman, Hans Vandierendonck, Koenraad De Bosschere. 207 [doi]
- DLP + TLP Processors for the Next Generation of Media WorkloadsJesús Corbal, Roger Espasa, Mateo Valero. 219-228 [doi]
- An Architectural Evaluation of Java TPC-WHarold W. Cain, Ravi Rajwar, Morris Marden, Mikko H. Lipasti. 229-240 [doi]
- A Programmable Co-Processor for ProfilingCraig B. Zilles, Gurindar S. Sohi. 241 [doi]
- A Delay Model and Speculative Architecture for Pipelined RoutersLi-Shiuan Peh, William J. Dally. 255-266 [doi]
- Quantifying the Impact of Architectural Scaling on CommunicationTaliver Heath, Samian Kaur, Richard P. Martin, Thu D. Nguyen. 267 [doi]
- Call Graph Prefetching for Database ApplicationsMurali Annavaram, Jignesh M. Patel, Edward S. Davidson. 281 [doi]
- Branch History Guided Instruction PrefetchingViji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak. 291-300 [doi]
- Reducing DRAM Latencies with an Integrated Memory Hierarchy DesignWei-Fen Lin, Steven K. Reinhardt, Doug Burger. 301-312 [doi]