Abstract is missing.
- Intel s Tera-scale Computing Project: The first five years, the next five yearsJoe Rattner. 1 [doi]
- Design and implementation of the blue gene/P snoop filterValentina Salapura, Matthias A. Blumrich, Alan Gara. 5-14 [doi]
- Fabric convergence implications on systems architectureKevin Leigh, Parthasarathy Ranganathan, Jaspal Subhlok. 15-26 [doi]
- Prediction of CPU idle-busy activity patternQian Diao, Justin J. Song. 27-36 [doi]
- Performance-aware speculation control using wrong path usefulness predictionChang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt. 39-49 [doi]
- PaCo: Probability-based path confidence predictionKshitiz Malik, Mayank Agarwal, Vikram Dhar, Matthew I. Frank. 50-61 [doi]
- Branch-mispredict level parallelism (BLP) for control independenceKshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin M. Woley, Matthew I. Frank. 62-73 [doi]
- Address-branch correlation: A novel locality for long-latency hard-to-predict branchesHongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zhou. 74-85 [doi]
- EXCES: External caching in energy saving storage systemsLuis Useche, Jorge Guerra, Medha Bhadkamkar, Mauricio Alarcon, Raju Rangaswami. 89-100 [doi]
- Cluster-level feedback power control for performance optimizationXiaorui Wang, Ming Chen. 101-110 [doi]
- C-Oracle: Predictive thermal management for data centersLuiz Ramos, Ricardo Bianchini. 111-122 [doi]
- System level analysis of fast, per-core DVFS using on-chip switching regulatorsWonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, David Brooks. 123-134 [doi]
- PEEP: Exploiting predictability of memory dependences in SMT processorsSamantika Subramaniam, Milos Prvulovic, Gabriel H. Loh. 137-148 [doi]
- Runahead Threads to improve SMT performanceTanausĂș RamĂrez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero. 149-158 [doi]
- Single-level integrity and confidentiality protection for distributed shared memory multiprocessorsBrian Rogers, Chenyu Yan, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin. 161-172 [doi]
- FlexiTaint: A programmable accelerator for dynamic taint propagationGuru Venkataramani, Ioannis Doudalis, Yan Solihin, Milos Prvulovic. 173-184 [doi]
- Amdahl s Law in the multicore eraMark D. Hill. 187 [doi]
- CMP network-on-chip overlaid with multi-band RF-interconnectM. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam. 191-202 [doi]
- Regional congestion awareness for load balance in networks-on-chipPaul Gratz, Boris Grot, Stephen W. Keckler. 203-214 [doi]
- Performance and power optimization through data compression in Network-on-Chip architecturesReetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijay Narayanan, Ravishankar Iyer, Mazin S. Yousif, Chita R. Das. 215-225 [doi]
- Automated microprocessor stressmark generationAjay M. Joshi, Lieven Eeckhout, Lizy Kurian John, Ciji Isen. 229-239 [doi]
- Roughness of microarchitectural design topologies and its implications for optimizationBenjamin C. Lee, David M. Brooks. 240-251 [doi]
- Fundamental performance constraints in horizontal fusion of in-order coresPierre Salverda, Craig B. Zilles. 252-263 [doi]
- Serializing instructions in system-intensive workloads: Amdahl s Law strikes againPhilip M. Wells, Gurindar S. Sohi. 264-275 [doi]
- Thread-safe dynamic binary translation using transactional memoryJaeWoong Chung, Michael Dalton, Hari Kannan, Christos Kozyrakis. 279-289 [doi]
- Uncovering hidden loop level parallelism in sequential applicationsHongtao Zhong, Mojtaba Mehrara, Steven A. Lieberman, Scott A. Mahlke. 290-301 [doi]
- A comprehensive approach to DRAM power managementIbrahim Hur, Calvin Lin. 305-316 [doi]
- Power-Efficient DRAM SpeculationNidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, James E. Smith. 317-328 [doi]
- High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulationRichard H. Larson, John K. Salmon, Ron O. Dror, Martin M. Deneroff, Cliff Young, John P. Grossman, Yibing Shan, John L. Klepeis, David E. Shaw. 331-342 [doi]
- Incorporating flexibility in Anton, a specialized machine for molecular dynamics simulationJeffrey Kuskin, Cliff Young, John P. Grossman, Brannon Batson, Martin M. Deneroff, Ron O. Dror, David E. Shaw. 343-354 [doi]
- An OS-based alternative to full hardware coherence on tiled CMPsChristian Fensch, Marcelo Cintra. 355-366 [doi]
- Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systemsJiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, Xiaodong Zhang, P. Sadayappan. 367-378 [doi]
- DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processorsMeeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David M. Brooks. 381-392 [doi]
- Supporting highly-decoupled thread-level redundancy for parallel programsM. Wasiur Rashid, Michael C. Huang. 393-404 [doi]
- Speculative instruction validation for performance-reliability trade-offSumeet Kumar, Aneesh Aggarwal. 405-414 [doi]
- Runtime validation of memory ordering using constraint graph checkingKaiyu Chen, Sharad Malik, Priyadarsan Patra. 415-426 [doi]
- Compilers and parallel computing systemsFrances Allen. 429 [doi]