Abstract is missing.
- XSpeed: Accelerating Reachability Analysis on Multi-core ProcessorsRajarshi Ray, Amit Gurung, Binayak Das, Ezio Bartocci, Sergiy Bogomolov, Radu Grosu. 3-18 [doi]
- Abstraction-Based Parameter Synthesis for Multiaffine SystemsSergiy Bogomolov, Christian Schilling, Ezio Bartocci, Grégory Batt, Hui Kong, Radu Grosu. 19-35 [doi]
- Combining Static and Dynamic Analyses for Vulnerability Detection: Illustration on HeartbleedBalázs Kiss, Nikolai Kosmatov, Dillon Pariente, Armand Puccetti. 39-50 [doi]
- The Verification Cockpit - Creating the Dream Playground for Data Analytics over the Verification ProcessMoab Arar, Michael L. Behm, Odellia Boni, Raviv Gal, Alex Goldin, Maxim Ilyaev, Einat Kermany, John R. Reysa, Bilal Saleh, Klaus-Dieter Schubert, Gil Shurek, Avi Ziv. 51-66 [doi]
- Coverage-Driven Verification - An Approach to Verify Code for Robots that Directly Interact with HumansDejanira Araiza-Illan, David Western, Anthony G. Pipe, Kerstin Eder. 69-84 [doi]
- PANDA: Simultaneous Predicate Abstraction and Concrete ExecutionJakub Daniel, Pavel Parizek. 87-103 [doi]
- TSO to SC via Symbolic ExecutionHeike Wehrheim, Oleg Travkin. 104-119 [doi]
- Parallel Symbolic Execution: Merging In-Flight RequestsMartin Nowack, Katja Tietze, Christof Fetzer. 120-135 [doi]
- Limited Mobility, Eventual StabilityLenore D. Zuck, Sanjiva Prasad. 139-154 [doi]
- A New Refinement Strategy for CEGAR-Based Industrial Model CheckingMartin Leucker, Grigory Markin, Martin R. Neuhäußer. 155-170 [doi]
- Quasi-equal Clock Reduction: Eliminating Assumptions on NetworksChristian Herrera, Bernd Westphal. 173-189 [doi]
- Resource-Parameterized Timing Analysis of Real-Time SystemsJin Hyun Kim, Axel Legay, Kim Guldstrand Larsen, Marius Mikucionis, Brian Nielsen. 190-205 [doi]
- SAT-Based Explicit LTL ReasoningJianwen Li, Shufang Zhu, Geguang Pu, Moshe Y. Vardi. 209-224 [doi]
- Understanding VSIDS Branching Heuristics in Conflict-Driven Clause-Learning SAT SolversJia Hui Liang, Vijay Ganesh, Ed Zulkoski, Atulan Zaman, Krzysztof Czarnecki. 225-241 [doi]
- Multi-Domain Verification of Power, Clock and Reset DomainsPing Yeung, Eugene Mandel. 245-255 [doi]
- FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and CorrectionAndrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne. 259-275 [doi]
- On Switching Aware Synthesis for Combinational CircuitsJan Láník, Oded Maler. 276-291 [doi]