Abstract is missing.
- Recent additions to the ARMv7-A architectureDavid Brash. [doi]
- Computational models for the age of multicore processingWolfgang Paul. [doi]
- Automotive embedded driver assistance: A real-time low-power FPGA stereo engine using semi-global matchingFelix Eberli. [doi]
- Welcome to ICCD 2010!Peter-Michael Seidel, Georgi Gaydadjiev, Sofiène Tahar, Lars J. Svensson. [doi]
- Out-of-order retirement of instructions in sequentially consistent multiprocessorsRafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, David R. Kaeli. 1-8 [doi]
- Efficient MIMD architectures for high-performance ray tracingDaniel Kopta, Josef B. Spjut, Erik Brunvand, Al Davis. 9-16 [doi]
- A study on performance benefits of core morphing in an asymmetric multicore processorAnup Das, Rance Rodrigues, Israel Koren, Sandip Kundu. 17-22 [doi]
- Lowering the latency of interfaces for rationally-related frequenciesJean-Michel Chabloz, Ahmed Hemani. 23-30 [doi]
- High throughput, low set-up time, reconfigurable linear Feedback Shift RegistersRick J. M. Nas, C. H. van Berkel. 31-37 [doi]
- Robust and energy-efficient DSP systems via output probability processingRami A. Abdallah, Naresh R. Shanbhag. 38-44 [doi]
- Optimization of back pressure and throughput for latency insensitive systemsBin Xue, Sandeep K. Shukla. 45-51 [doi]
- QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round RobinYue Qian, Zhonghai Lu, Qiang Dou. 52-59 [doi]
- A flexible simulation methodology and tool for nanoarray-based architecturesStefano Frache, Mariagrazia Graziano, Maurizio Zamboni. 60-67 [doi]
- Elaboration-time synthesis of high-level language constructs in SystemC-based microarchitectural simulatorsZhuo Ruan, Kurtis Cahill, David A. Penry. 68-75 [doi]
- Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithmsRami Sheikh, Mazen Kharbutli. 76-83 [doi]
- Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessorsAli Shafiee, Narges Shahidi, Amirali Baniasadi. 84-91 [doi]
- A tag-based cache replacementChuanjun Zhang, Bing Xue. 92-97 [doi]
- A voting-based working set assessment scheme for dynamic cache resizing mechanismsMasayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 98-105 [doi]
- Insertion policy selection using Decision Tree AnalysisSamira Manabi Khan, Daniel A. Jiménez. 106-111 [doi]
- Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECCShi-Ting Zhou, Sumeet Katariya, Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim. 112-117 [doi]
- Thermal-aware scratchpad memory design and allocationMorteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal. 118-124 [doi]
- Spintronic logic gates for spintronic data using magnetic tunnel junctionsShruti Patil, Andrew Lyle, Jonathan Harms, David J. Lilja, Jian-Ping Wang. 125-131 [doi]
- On mismatch number distribution of nanocrossbar logic mappingYehua Su, Wenjing Rao. 132-137 [doi]
- Sub-threshold charge recovery circuitsMehrdad Khatir, Hassan Ghasemzadeh Mohammadi, Alireza Ejlali. 138-144 [doi]
- Data rate maximization by adaptive thresholding RF power management under renewable energyWeiguo Tang, Lei Wang. 145-150 [doi]
- Practical completion detection for 2-of-N delay-insensitive codesMarco Cannizzaro, WeiWei Jiang, Steven M. Nowick. 151-158 [doi]
- Rate-monotonic scheduling for reducing system-wide energy consumption for hard real-time systemsLinwei Niu. 159-165 [doi]
- Design and implementation of a special purpose embedded system for neural machine interfaceXiaorong Zhang, He Huang, Qing Yang. 166-172 [doi]
- A control-theoretic energy management for fault-tolerant hard real-time systemsAli Sharif Ahmadian, Mahdieh Hosseingholi, Alireza Ejlali. 173-178 [doi]
- RTOS-aware modeling of embedded hardware/software systemsMatthias Müller, Joachim Gerlach, Wolfgang Rosenstiel. 179-186 [doi]
- Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systemsPaolo Burgio, Martino Ruggiero, Francesco Esposito, Mauro Marinoni, Giorgio C. Buttazzo, Luca Benini. 187-194 [doi]
- The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithmsGlauco Borges Valim dos Santos, Tiago Reimann, Marcelo de Oliveira Johann, Ricardo Reis. 195-202 [doi]
- Routability-driven flip-flop merging process for clock power reductionZhi-Wei Chen, Jin-Tai Yan. 203-208 [doi]
- Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory arrayVinayak Honkote, Baris Taskin. 209-214 [doi]
- Incremental gate sizing for late process changesJohn Lee, Puneet Gupta. 215-221 [doi]
- Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimizationSanghamitra Roy, Koushik Chakraborty. 222-228 [doi]
- Boolean factoring with multi-objective goalsMayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis. 229-234 [doi]
- A simple pipelined logarithmic multiplierPatricio Bulic, Zdenka Babic, Aleksej Avramovic. 235-240 [doi]
- A radix-10 digit recurrence division unit with a constant digit selection functionMalte Baesler, Sven-Ole Voigt, Thomas Teufel. 241-246 [doi]
- A unified addition structure for moduli set {2:::n:::-1, 2:::n:::, 2:::n:::+1} based on a novel RNS representationSomayeh Timarchi, Mahmood Fazlali, Sorin Cotofana. 247-252 [doi]
- Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithmsShohreh Sharif Mansouri, Elena Dubrova. 253-259 [doi]
- VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architectureVaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy. 260-265 [doi]
- Combined optimal and heuristic approaches for multiple constant multiplicationJason Thong, Nicola Nicolici. 266-273 [doi]
- Threads vs. caches: Modeling the behavior of parallel workloadsZvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser. 274-281 [doi]
- Predicting the throughput of multiprocessor applications under dynamic workloadPeter Poplavko, Marc Geilen, Twan Basten. 282-288 [doi]
- M5 based EDGE architecture modelingPengfei Gou, Qingbo Li, Yinghan Jin, Qi Zheng, Bing Yang, Mingyan Yu, Jinxiang Wang. 289-296 [doi]
- A lightweight run-time scheduler for multitasking multicore stream applicationsMichael A. Baker, Karam S. Chatha. 297-304 [doi]
- Scenario-based design space exploration of MPSoCsPeter van Stralen, Andy D. Pimentel. 305-312 [doi]
- Toward reliable SRAM-based device identificationJoonsoo Kim, Joonsoo Lee, Jacob A. Abraham. 313-320 [doi]
- DSS: Applying asynchronous techniques to architectures exploiting ILP at compile timeWei Shi, Zhiying Wang, Hongguang Ren, Ting Cao, Wei Chen 0009, Bo Su, Hongyi Lu. 321-327 [doi]
- Using variable clocking to reduce leakage in synchronous circuitsNavid Toosizadeh, Safwat G. Zaky, Jianwen Zhu. 328-335 [doi]
- Efficient provably good OPC modeling and its applications to interconnect optimizationShih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang. 336-341 [doi]
- Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALUSeokin Hong, Soontae Kim. 342-349 [doi]
- Feasibility study of dynamic Trusted Platform ModuleArun K. Kanuparthi, Mohamed Zahran, Ramesh Karri. 350-355 [doi]
- Optimal power/performance pipelining for error resilient processorsNicolas Zea, John Sartori, Ben Ahrens, Rakesh Kumar. 356-363 [doi]
- Implicit hints: Embedding hint bits in programs without ISA changesHans Vandierendonck, Koen De Bosschere. 364-369 [doi]
- Countering code injection attacks with TLB and I/O monitoringDongkyun Ahn, Gyungho Lee. 370-375 [doi]
- Energy optimal on-line Self-Test of microprocessors in WSN nodesAndreas Merentitis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis. 376-383 [doi]
- Temperature-to-power mappingZhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan. 384-389 [doi]
- Delay test quality maximization through process-aware selection of test set sizeBaris Arslan, Alex Orailoglu. 390-395 [doi]
- Crosstalk modeling to predict channel delay in Network-on-ChipsAhmad Patooghy, Seyed Ghassem Miremadi, Mansour Shafaei. 396-401 [doi]
- Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debuggingYeonbok Lee, Takeshi Matsumoto, Masahiro Fujita. 402-408 [doi]
- An energy model for graphics processing unitsJeff Pool, Anselmo Lastra, Montek Singh. 409-416 [doi]
- LMS-based low-complexity game workload prediction for DVFSBenedikt Dietrich, Swaroop Nunna, Dip Goswami, Samarjit Chakraborty, Matthias Gries. 417-424 [doi]
- Exploiting SIMD extensions for linear image processing with OpenCLSamuel Antao, Leonel Sousa. 425-430 [doi]
- A co-processor approach for accelerating data-structure intensive algorithmsJason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden. 431-438 [doi]
- SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOSTushar Krishna, Jacob Postman, Christopher Edmonds, Li-Shiuan Peh, Patrick Chiang. 439-446 [doi]
- A fine-grained link-level fault-tolerant mechanism for networks-on-chipArseniy Vitkovskiy, Vassos Soteriou, Chrysostomos Nicopoulos. 447-454 [doi]
- Bandwidth optimization in asynchronous NoCs by customizing link wire lengthJunBok You, Daniel Gebhardt, Kenneth S. Stevens. 455-461 [doi]
- A high performance router with dynamic buffer allocation for on-chip interconnect networksShubo Qi, Minxuan Zhang, Jinwen Li, Tianlei Zhao, Chengyi Zhang, Shaoqing Li. 462-467 [doi]
- DDPSL: An easy way of defining propertiesLuigi Di Guglielmo, Franco Fummi, Nicola Orlandi, Graziano Pravadelli. 468-473 [doi]
- DfT optimization for pre-bond testing of 3D-SICs containing TSVsJia Li, Dong Xiang. 474-479 [doi]
- Efficient test response compaction for robust BIST using parity sequencesThomas Indlekofer, Michael Schnittger, Sybille Hellebrand. 480-485 [doi]
- EQUIPE: Parallel equivalence checking with GP-GPUsDebapriya Chatterjee, Valeria Bertacco. 486-493 [doi]
- Identifying optimal generic processors for biomedical implantsChristos Strydis, Dhara Dave. 494-501 [doi]
- Exploiting application-dependent ambient temperature for accurate architectural simulationHyung Beom Jang, Jinhang Choi, Ikroh Yoon, Sung-Soo Lim, Seungwon Shin, Naehyuck Chang, Sung Woo Chung. 502-508 [doi]
- Inter-socket victim cacheing for platform power reductionSubhra Mazumdar, Dean M. Tullsen, Justin J. Song. 509-514 [doi]
- Dynamic register file partitioning in superscalar microprocessors for energy efficiencyMeltem Ozsoy, Yusuf Onur Koçberber, Mehmet Kayaalp, Oguz Ergin. 515-520 [doi]
- Package-Aware Scheduling of embedded workloads for temperature and Energy management on heterogeneous MPSoCsShervin Sharifi, Tajana Simunic Rosing. 521-527 [doi]
- Towards cool and reliable digital systems: RT level CED techniques with runtime adaptabilityYu Liu, Kaijie Wu. 528-533 [doi]
- IP characterization methodology for fast and accurate power consumption estimation at transactional level modelMichel Rogers-Vallée, Marc-André Cantin, Laurent Moss, Guy Bois. 534-541 [doi]
- Enhancing dual-Vt design with consideration of on-chip temperature variationJunjun Gu, Gang Qu, Lin Yuan. 542-547 [doi]
- BDD-based circuit restructuring for reducing dynamic powerQuang Dinh, Deming Chen, Martin D. F. Wong. 548-554 [doi]