Table of Contents

• Reading Between the Dies: Cross-SLR Covert Channels on Multi-Tenant Cloud FPGAsIlias Giechaskiel, Kasper Rasmussen, Jakub Szefer. 1-10 [doi]
• IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip DesignQicheng Huang, Chenlei Fang, Zeye Liu 0001, Ruizhou Ding, R. D. Shawn Blanton. 11-19 [doi]
• Stealthy Rootkits in Smart Grid ControllersPrashanth Krishnamurthy, Hossein Salehghaffari, Shiva Duraisamy, Ramesh Karri, Farshad Khorrami. 20-28 [doi]
• Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition StrategyChiou-Yng Lee, Jiafeng Xie. 29-37 [doi]
• An FPGA Implementation of Stochastic Computing-Based LSTMGuy Maor, Xiaoming Zeng, Zhendong Wang, Yang Hu. 38-46 [doi]
• Process Variation Mitigation on Convolutional Neural Network Accelerator ArchitectureMaodi Ma, Jingweijia Tan, Xiaohui Wei, Kaige Yan. 47-55 [doi]
• Characterizing On-Chip Traffic Patterns in General-Purpose GPUs: A Deep Learning ApproachYunfan Li, Drew Penney, Abhishek Ramamurthy, Lizhong Chen. 56-64 [doi]
• AccUDNN: A GPU Memory Efficient Accelerator for Training Ultra-Deep Neural NetworksJinrong Guo, Wantao Liu, Wang Wang, Chunrong Yao, Jizhong Han, Ruixuan Li, Yijun Lu, Songlin Hu. 65-72 [doi]
• A Distributed Scheme for Accelerating Semantic Video Segmentation on An Embedded ClusterHsuan-Kung Yang, Tsu-Jui Fu, Po-Han Chiang, Kuan-Wei Ho, Chun-Yi Lee. 73-81 [doi]
• TiLA: Twin-in-the-Loop Architecture for Cyber-Physical Production SystemsHeeJong Park 0001, Arvind Easwaran, Sidharta Andalam. 82-90 [doi]
• RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its LifetimeWen Li, Ying Wang 0001, Huawei Li, Xiaowei Li 0001. 91-99 [doi]
• WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based ComputersJunichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai. 100-108 [doi]
• Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write BandwidthMainak Chaudhuri, Jayesh Gaur, Sreenivas Subramoney. 109-118 [doi]
• To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM CachesVinson Young, Moinuddin K. Qureshi. 119-128 [doi]
• Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source CodeGeorgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi. 129-137 [doi]
• A New Traffic Offloading Method with Slow Switching Optical Device in Exascale ComputerEn Shao, Guangming Tan, Zhan Wang, Guojun Yuan, Ninghui Sun. 138-146 [doi]
• ReRAM Crossbar-Based Analog Computing Architecture for Naive Bayesian EngineBing Wu, Dan Feng 0001, Wei Tong, Jingning Liu, Chengning Wang, Wei Zhao, Mengye Peng. 147-155 [doi]
• HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGASayed Abdolrasouol Faraji, Gaurav Singh, Kia Bazargan. 156-163 [doi]
• Hardware Acceleration of Multilayer Perceptron Based on Inter-Layer OptimizationShenggang Chen, Zhonghai Lu. 164-172 [doi]
• NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks AcceleratorGaoming Du, Zhenwen Yang, Zhenmin Li, Duoli Zhang, Yong-Sheng Yin, Zhonghai Lu. 173-176 [doi]
• A Memory-Access-Efficient Adaptive Implementation of kNN on FPGA through HLSXiaojia Song, Tao Xie 0004, Stephen Fischer. 177-180 [doi]
• Adaptive Write Interference Management with Efficient Mapping for Shingled Recording DisksMing-Chang Lee, Li-Pin Chang, Sung-Ming Wu, Wei-Shang Yui. 181-189 [doi]
• RepEC-Duet: Ensure High Reliability and Performance for Deduplicated and Delta-Compressed Storage SystemsChunxue Zuo, Fang Wang 0001, Ping Huang, Yuchong Hu, Dan Feng 0001. 190-198 [doi]
• Lifelong Disk Failure Prediction via GAN-Based Anomaly DetectionTianming Jiang, Jiangfeng Zeng, Ke Zhou 0001, Ping Huang 0001, Tianming Yang. 199-207 [doi]
• An Efficient and Flexible Metadata Management Layer for Local File SystemsYubo Liu, Hongbo Li, Yutong Lu, Zhiguang Chen, Ming Zhao. 208-216 [doi]
• Security-Driven Codesign with Weakly-Hard Constraints for Real-Time Embedded SystemsHengyi Liang, Zhilu Wang, Debayan Roy, Soumyajit Dey, Samarjit Chakraborty, Qi Zhu 0002. 217-226 [doi]
• Software Timing Analysis for Complex Hardware with Survivability and Risk AnalysisSergi Vilardell, Isabel Serra, Jaume Abella, Joan del Castillo, Francisco J. Cazorla. 227-236 [doi]
• Integrating Cyber-Attack Defense Techniques into Real-Time Cyber-Physical SystemsXiaochen Hao, Mingsong Lv, Jiesheng Zheng, Zhengkui Zhang, Wang Yi 0001. 237-245 [doi]
• Astraea: Self-Balancing Federated Learning for Improving Classification Accuracy of Mobile Deep Learning ApplicationsMoming Duan, Duo Liu, Xianzhang Chen, Yujuan Tan, Jinting Ren, Lei Qiao, Liang Liang 0002. 246-254 [doi]
• A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCsTimon Evenblij, Christian Tenllado, Manu Perumkunnil, Francky Catthoor, Sushil Sakhare, Peter Debacker, Gouri Sankar Kar, Arnaud Furnémont, Nicolas Bueno, José Ignacio Gómez Pérez. 255-263 [doi]
• NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data CacheNezam Rohbani, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka. 264-272 [doi]
• SpecLock: Speculative Lock ForwardingPooria M. Yaghini, George Michelogiannakis, Paul V. Gratz. 273-282 [doi]
• Fine-Grained Management of Thread Blocks for Irregular ApplicationsJonathan Beaumont, Trevor N. Mudge. 283-292 [doi]
• Red Teaming a Multi-Colored Bluetooth BulbRyan Vrecenar, Michael Hall, Joshua Zshiesche, Mahesh Naidu, Jeyavijayan Rajendran, Stavros Kalafatis. 293-296 [doi]
• Bridging The Gap: Data Exfiltration In Highly Secured Environments Using Bluetooth IoTsEleonore Carpentier, Corentin Thomasset, Jérémy Briffaut. 297-300 [doi]
• Covert Data Exfiltration Using Light and Power ChannelsPatrick Cronin, Charles Gouert, Dimitris Mouris, Nektarios Georgios Tsoutsos, Chengmo Yang. 301-304 [doi]
• Post-Model Validation of Victim DRAM CachesDebiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam. 305-308 [doi]
• Revisiting Capacitor-Based Trojan DesignMohammad-Mahdi Bidmeshki, Kiruba Sankaran Subramani, Yiorgos Makris. 309-312 [doi]
• Formal Modeling and Verification of NAND Flash Memory Supporting Advanced OperationsShivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Srinivas Pinisetty. 313-316 [doi]
• SaberX4: High-Throughput Software Implementation of Saber Key Encapsulation MechanismSujoy Sinha Roy. 321-324 [doi]
• Advances and Challenges of Rank Metric Cryptography ImplementationsEmanuele Bellini 0002, Florian Caullery, Rusydi H. Makarim, Marc Manzano, Chiara Marcolla, Víctor Mateu. 325-328 [doi]
• Flexible NTT Accelerators for RLWE Lattice-Based CryptographyHamid Nejatollahi, Rosario Cammarota, Nikil D. Dutt. 329-332 [doi]
• PlaidML-HE: Acceleration of Deep Learning Kernels to Compute on Encrypted DataHuili Chen, Rosario Cammarota, Felipe Valencia, Francesco Regazzoni. 333-336 [doi]
• Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design FlowDeepraj Soni, Mohammed Nabeel, Kanad Basu, Ramesh Karri. 337-340 [doi]
• TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory SystemsVinson Young, Zeshan A. Chishti, Moinuddin K. Qureshi. 341-349 [doi]
• Static Function Prefetching for Efficient Code Management on Scratchpad MemoryYoungbin Kim, Kyoungwoo Lee, Aviral Shrivastava. 350-358 [doi]
• Low Power Design through Frequency-Optimized Runtime Micro-Architectural AdaptationJianqi Chen, Benjamin Carrión Schäfer. 359-366 [doi]
• HiNUMA: NUMA-Aware Data Placement and Migration in Hybrid Memory SystemsZhuohui Duan, Haikun Liu, Xiaofei Liao, Hai Jin 0001, Wenbin Jiang, Yu Zhang 0027. 367-375 [doi]
• FPGA Energy Efficiency by Leveraging Thermal MarginBehnam Khaleghi, Sahand Salamat, Mohsen Imani, Tajana Rosing. 376-384 [doi]
• A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell DesignMohammed Salman Ahmed, Zia Abbas. 385-392 [doi]
• CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network ApproachMohammad Saeed Abrishami, Massoud Pedram, Shahin Nazarian. 393-400 [doi]
• Exploiting the Benefits of High-Level Synthesis for Thermal-Aware VLSI DesignJianqi Chen, Benjamin Carrión Schäfer. 401-404 [doi]
• Efficient Linear System Solution Techniques in the Simulation of Large Dense Mutually Inductive CircuitsCharalampos Antoniadis, Milan Mihajlovic, Nestor E. Evmorfopoulos, Georgios I. Stamoulis, Vasilis F. Pavlidis. 405-408 [doi]
• System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-ChipsJan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck. 409-412 [doi]
• Constraint-Programmed Initial Sizing of Analog Operational AmplifiersInga Abel, Maximilian Neuner, Helmut Graeb. 413-421 [doi]
• Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBsLing-Yen Song, Yi-ling Chen, Yung-Chun Lei, Juinn-Dar Huang. 422-428 [doi]
• A Buffer and Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting CircuitsRuizhe Cai, Olivia Chen, Ao Ren, Ning Liu 0007, Nobuyuki Yoshikawa, Yanzhi Wang. 429-436 [doi]
• PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip NetworksCheng Tan, Yanghui Ou, Shunning Jiang, Peitian Pan, Christopher Torng, Shady Agwa, Christopher Batten. 437-445 [doi]
• qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification FrameworkShahin Nazarian, Arash Fayyazi, Massoud Pedram. 446-449 [doi]
• A Learning-Based Framework for Automatic Parameterized VerificationYongjian Li, Jialun Cao, Jun Pang 0001. 450-459 [doi]
• Learning-Based Diversity Estimation: Leveraging the Power of High-Level Synthesis to Mitigate Common-Mode FailureFarah Naz Taher, Anjana Balachandran, Benjamin Carrión Schäfer. 460-467 [doi]
• Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model Based Re-usability PredictorAvishek Choudhury, Biplab K. Sikdar. 468-476 [doi]
• ReNEW: Enhancing Lifetime for ReRAM Crossbar Based Neural Network AcceleratorsWen Wen, Youtao Zhang, Jun Yang 0002. 487-496 [doi]
• Ebird: Elastic Batch for Improving Responsiveness and Throughput of Deep Learning ServicesWeihao Cui, Mengze Wei, Quan Chen 0002, Xiaoxin Tang, Jingwen Leng, Li Li, Mingyi Guo. 497-505 [doi]
• When Deep Learning Meets the Edge: Auto-Masking Deep Neural Networks for Efficient Machine Learning on Edge DevicesNing Lin, Hang Lu, Xing Hu, Jingliang Gao, Mingzhe Zhang, Xiaowei Li 0001. 506-514 [doi]
• A High-Performance Processing-in-Memory Accelerator for Inline Data DeduplicationYoung Seo Lee, Kyung Min Kim, Ji-Heon Lee, Jeong Hwan Choi, Sung Woo Chung. 515-523 [doi]
• Low Power Design of Runtime Reconfigurable FPGAs through Contexts ApproximationsSiyuan Xu, Benjamin Carrión Schäfer. 524-531 [doi]
• Applying Swarm Intelligence to Distributed On-Chip Power ManagementDivya Pathak, Ioannis Savidis. 532-540 [doi]
• FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-Based Memory ArrayXiaoyu Zhang, Xiaoming Chen 0003, Yinhe Han. 541-549 [doi]
• Threshold Logic in a FlashAnkit Wagle, Gian Singh, Jinghua Yang, Sunil Khatri, Sarma B. K. Vrudhula. 550-558 [doi]
• Adaptive Masking: a Dynamic Trade-off between Energy Consumption and Hardware SecurityMaxime Montoya, Thomas Hiscock, Simone Bacles-Min, Anca Molnos, Jacques Fournier. 559-566 [doi]
• Cyclic Beneš Network Based Logic Encryption for Mitigating SAT-Based AttacksSaranyu Chattopadhyay, Rajat Subhra Chakraborty. 567-575 [doi]
• PUF-RLA: A PUF-Based Reliable and Lightweight Authentication Protocol Employing Binary String ShufflingMahmood Azhar Qureshi, Arslan Munir. 576-584 [doi]
• AdapTimer: Hardware/Software Collaborative Timer Resistant to Flush-Based Cache Attacks on ARM-FPGA Embedded SoCJingquan Ge, Neng Gao, Chenyang Tu, Ji Xiang, Zeyi Liu. 585-593 [doi]
• Architectural and Cost Implications of the 5G Edge NFV SystemsYang Hu, Jianda Wang. 594-603 [doi]
• Imbalance-Aware Scheduler for Fast and Secure Ring ORAM Data RetrievalYuezhi Che, Yuan Hong, Rujia Wang. 604-612 [doi]
• SPA-SSD: Exploit Heterogeneity and Parallelism of 3D SLC-TLC Hybrid SSD to Improve Write PerformanceWenhui Zhang, Qiang Cao, Hong Jiang 0001, Jie Yao, Yuanyuan Dong, Puyuan Yang. 613-621 [doi]
• Mitigating Application Diversity for Allocating a Unified ACC-Rich PlatformJinghan Zhang, Hamed Tabkhi, Gunar Schirner. 622-625 [doi]
• VNet: A Versatile Network for Efficient Real-Time Semantic SegmentationNing Lin, Hang Lu, Jingliang Gao, Shunjie Qiao, Xiaowei Li 0001. 626-629 [doi]
• Energy Prediction for Cache Tuning in Embedded SystemsRuben Vazquez, Ann Gordon-Ross, Greg Stitt. 630-637 [doi]
• Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement LearningShaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura. 638-647 [doi]
• Dynamic Optimization of Battery Health in IoT NetworksKazim Ergun, Raid Ayoub, Pietro Mercati, Tajana Rosing. 648-655 [doi]
• BRASIL: A High-Integrity GPGPU Toolchain for Automotive SystemsMatina Maria Trompouki, Leonidas Kosmidis. 660-663 [doi]
• Balancing Performance and Energy Efficiency of ONoC by Using Adaptive BandwidthMingzhe Zhang, Lunkai Zhang, Frederic T. Chong, Zhiyong Liu. 664-667 [doi]
• VaLLR: Threshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND FlashLanlan Cui, Fei Wu 0005, Xiaojian Liu, Meng Zhang 0014, Changsheng Xie. 668-671 [doi]
• Reinforce Memory Error Protection by Breaking DRAM Disturbance Correlation Within ECC WordsYicheng Wang, Yang Liu 0114, Peiyun Wu, Zhao Zhang 0008. 672-675 [doi]
• Archivist: A Machine Learning Assisted Data Placement Mechanism for Hybrid Storage SystemsJinting Ren, Xianzhang Chen, Yujuan Tan, Duo Liu, Moming Duan, Liang Liang 0002, Lei Qiao. 676-679 [doi]
• Detecting and Predicting Performance Degradation Caused by Impaired Cache IsolationYi Zhang 0056, Zhanwei Ling, Ran Cui, Mingsong Lv, Nan Guan, Qingxu Deng. 680-683 [doi]
• A Case for Software-Based Adaptive Routing in NUMA SystemsWonJun Song, John Kim. 684-693 [doi]
• Value Speculation through Equality PredictionKleovoulos Kalaitzidis, André Seznec. 694-697 [doi]
• A Novel Convolutional Neural Network Accelerator That Enables Fully-Pipelined Execution of LayersDonghyun Kang, Jintaek Kang, Hyungdal Kwon, Hyunsik Park, Soonhoi Ha. 698-701 [doi]
• Freeflow Core: Enhancing Performance of In-Order Cores with Energy EfficiencyRaj Kumar Choudhary, Newton Singh, Harideep Nair, Rishabh Rawat, Virendra Singh. 702-705 [doi]