Abstract is missing.
- A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM MacroJunji Ogawa, Mark Horowitz. 1-14 [doi]
- Software Controlled Reconfigurable On-Chip Memory for High Performance ComputingHiroshi Nakamura, Masaaki Kondo, Taisuke Boku. 15-32 [doi]
- Content-Based Prefetching: Initial ResultsRobert Cooksey, Dennis Colarelli, Dirk Grunwald. 33-55 [doi]
- Memory System Support for Dynamic Cache Line AssemblyLixin Zhang, Venkata K. Pingali, Bharat Chandramouli, John B. Carter. 56-70 [doi]
- Adaptively Mapping Code in an Intelligent Memory ArchitectureYan Solihin, Jaejin Lee, Josep Torrellas. 71-84 [doi]
- The Characterization of Data Intensive Memory Workloads on Distributed PIM SystemsRichard C. Murphy, Peter M. Kogge, Arun Rodrigues. 85-103 [doi]
- Memory Management in a PIM-Based ArchitectureMary W. Hall, Craig S. Steele. 104-121 [doi]
- Exploiting On-Chip Memory Bandwidth in the VIRAM CompilerDavid Judd, Katherine A. Yelick, Christoforos E. Kozyrakis, David Martin, David A. Patterson. 122-134 [doi]
- FlexCache: A Framework for Flexible Compiler Generated Data CachingCsaba Andras Moritz, Matthew Frank, Saman P. Amarasinghe. 135-146 [doi]
- Aggressive Memory-Aware CompilationPeter Grun, Nikil D. Dutt, Alexandru Nicolau. 147-151 [doi]
- Energy/Performance Design of Memory Hierarchies for Processor-in-Memory ChipsMichael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas. 152-159 [doi]
- SAGE: A New Analysis and Optimization System for FlexRAM ArchitectureTsung-Chuan Huang, Slo-Li Chu. 160-168 [doi]
- Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory SystemsKoji Inoue, Koji Kai, Kazuaki Murakami. 169-178 [doi]
- The DIVA Emulator: Accelerating Architecture Studies for PIM-Based SystemsJeff La Coss. 179-182 [doi]
- Compiler-Directed Cache Line Size AdaptivityDan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta. 183-187 [doi]
- Workshop Notes188-192 [doi]