Abstract is missing.
- Architecture of a Hardware Data InterpreterYaohan Chu. 1-9
- The Design of Some Language Constructs for Horizontal MicroprogrammingSubrata Dasgupta, Simon Fraser. 10-16
- The Honeywell Modular Microprogram Machine: M3E. Douglas Jensen, Richard Y. Kain. 17-28
- A Multi-Microprocessor Implementation of a General Purpose Pipelined CPURichard R. Ramseyer, Andries van Dam. 29-34
- Hierarchical Multiprocessor OrganizationsJ. Archer Harris, David R. Smith. 41-48
- Poly-Processor System Analysis and DesignK. Murakami, S. Nishikawa, M. Soto. 49-56
- A Few Examples of How to Use a Symmetrical Multi-Micro-ProcessorGuy Mazaré. 57-62
- The Microprogramming of Pipelined ProcessorsPeter M. Kogge. 63-70
- The Universality of Various Types of SIMD Machine Interconnection NetworksHoward Jay Siegel. 70-79
- The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction UnitsB. Ramakrishna Rau, George E. Rossman. 80-89
- The Architecture of an ALGOL 60 Computer Implemented with Distributed ProcessorsLeonard S. Haynes. 95-104
- A Large Scale, Homogeneous, Fully Distributed Parallel Machine, IHerbert Sullivan, Theodore R. Bashkow. 105-117
- A Large Scale, Homogeneous, Fully Distributed Parallel Machine, IIHerbert Sullivan, Theodore R. Bashkow, David Klappholz. 118-124
- On Virtual Memories and MicronetworksG. Jack Lipovski. 125-134
- Considerations for New Tactical Computer SystemsJon C. Strauss, Kenneth J. Thurber. 135-140
- An Advanced Tactical Computer ConceptKenneth J. Thurber, Peter C. Patton, Robert C. Deward, Jon C. Strauss, Thomas W. Petschauer. 141-146
- The Design and Implementation of a Real-Time Sound Generation SystemPaul E. Dworak, Alice C. Parker, Richard Blum. 153-158
- Hardware/Software Tradeoffs in A Variable Word Width, Variable Queue Length Buffer MemoryAlice C. Parker, Andrew W. Nagle. 159-164
- An Instruction Timing Model of CPU PerformanceBernard L. Peuto, Leonard J. Shustek. 165-178
- Information Content of CPU Memory Referencing BehaviorDan W. Hammerstrom, Edward S. Davidson. 184-192
- Message Communication Protocol and Operation System Design for the Distributed Loop Computer Network (DLCN)Ming T. Liu, Cecil C. Reames. 193-200
- High-Speed Buffering for Variable Length OperandsH. L. Tredennick, Terry A. Welch. 205-210