Table of Contents

• A Configurable Cloud-Scale DNN Processor for Real-Time AIJeremy Fowers, Kalin Ovtcharov, Michael Papamichael, Todd Massengill, Ming Liu, Daniel Lo, Shlomi Alkalay, Michael Haselman, Logan Adams, Mahdi Ghandi, Stephen Heil, Prerak Patel, Adam Sapek, Gabriel Weisz, Lisa Woods, Sitaram Lanka, Steven K. Reinhardt, Adrian M. Caulfield, Eric S. Chung, Doug Burger. 1-14 [doi]
• Virtual Melting Temperature: Managing Server Load to Minimize Cooling Overhead with Phase Change MaterialsMatt Skach, Manish Arora, Dean M. Tullsen, Lingjia Tang, Jason Mars. 15-28 [doi]
• FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public CloudSagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, Krste Asanovic. 29-42 [doi]
• PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning AlgorithmsPrakalp Srivastava, Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Jungwook Choi, Vikram S. Adve, Nam Sung Kim, Naresh Shanbhag. 43-56 [doi]
• Computation Reuse in DNNs by Exploiting Input SimilarityMarc Riera, Jose-Maria Arnau, Antonio González 0001. 57-68 [doi]
• GenAx: A Genome Sequencing AcceleratorDaichi Fujiki, Arun Subramaniyan 0001, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy. 69-82 [doi]
• Division of Labor: A More Effective Approach to PrefetchingSushant Kondguli, Michael Huang. 83-95 [doi]
• Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache HierarchiesAnant Nori, Jayesh Gaur, Siddharth Rai, Sreenivas Subramoney, Hong Wang. 96-109 [doi]
• Rethinking Belady's Algorithm to Accommodate PrefetchingAkanksha Jain, Calvin Lin. 110-123 [doi]
• Constructing a Weak Memory ModelSizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind. 124-137 [doi]
• A Hardware Accelerator for Tracing Garbage CollectionMartin Maas, Krste Asanovic, John Kubiatowicz. 138-151 [doi]
• Charm: A Language for Closed-Form High-Level Architecture ModelingWeilong Cui, Yongshan Ding, Deeksha Dangwal, Adam Holmes, Joseph McMahan, Ali JavadiAbhari, Georgios Tzimpragos, Frederic T. Chong, Timothy Sherwood. 152-165 [doi]
• Get Out of the Valley: Power-Efficient Address Mapping for GPUsYuxi Liu, Xia Zhao, Magnus Jahre, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, Lieven Eeckhout. 166-179 [doi]
• Scheduling Page Table Walks for Irregular GPU ApplicationsSeunghee Shin, Guilherme Cox, Mark Oskin, Gabriel H. Loh, Yan Solihin, Abhishek Bhattacharjee, Arkaprava Basu. 180-192 [doi]
• SEESAW: Using Superpages to Improve VIPT CachesMayank Parasar, Abhishek Bhattacharjee, Tushar Krishna. 193-206 [doi]
• A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive MemoryNandita Vijaykumar, Abhilasha Jain, Diptesh Majumdar, Kevin Hsieh, Gennady Pekhimenko, Eiman Ebrahimi, Nastaran Hajinazar, Phillip B. Gibbons, Onur Mutlu. 207-220 [doi]
• Non-Speculative Store Coalescing in Total Store OrderAlberto Ros, Stefanos Kaxiras. 221-234 [doi]
• Dynamic Memory Dependence PredicationZhaoxiang Jin, Soner Önder. 235-246 [doi]
• ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic SpecificationsNicolai Oswald, Vijay Nagarajan, Daniel J. Sorin. 247-260 [doi]
• Spandex: A Flexible Interface for Efficient Heterogeneous CoherenceJohnathan Alsop, Matthew D. Sinclair, Sarita V. Adve. 261-274 [doi]
• Flexon: A Flexible Digital Neuron for Efficient Spiking Neural Network SimulationsDayeol Lee, Gwangmu Lee, Dongup Kwon, Sunghwa Lee, Youngsok Kim, Jangwoo Kim. 275-288 [doi]
• Space-Time Algebra: A Model for Neocortical ComputationJames Smith. 289-300 [doi]
• Architecting a Stochastic Computing Unit with Molecular Optical DevicesXiangyu Zhang, Ramin Bashizade, Craig LaBoda, Chris Dwyer, Alvin R. Lebeck. 301-314 [doi]
• Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level CacheKunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang. 315-327 [doi]
• ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-PredictionVinson Young, Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi. 328-339 [doi]
• RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAMFengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu, Shaojun Wei. 340-352 [doi]
• Scaling Datacenter Accelerators with Compute-Reuse ArchitecturesAdi Fuchs, David Wentzlaff. 353-366 [doi]
• Enabling Scientific Computing on Memristive AcceleratorsBen Feinberg, Uday Kumar Reddy Vengalam, Nathan Whitehair, Shibo Wang, Engin Ipek. 367-382 [doi]
• Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural NetworksCharles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan 0001, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das. 383-396 [doi]
• FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State DrivesArash Tavakkol, Mohammad Sadrosadati, Saugata Ghose, Jeremie Kim, Yixin Luo, Yaohua Wang, Nika Mansouri-Ghiasi, Lois Orosa, Juan Gómez-Luna, Onur Mutlu. 397-410 [doi]
• GraFBoost: Using Accelerated Flash Storage for External Graph AnalyticsSang-Woo Jun, Andy Wright, Sizhuo Zhang, Shuotao Xu, Arvind. 411-424 [doi]
• 2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State DrivesDuck-Ho Bae, Insoon Jo, Youra Choi, Joo Young Hwang, Sangyeun Cho, Daniel D. G. Lee, Jaeheon Jeong. 425-438 [doi]
• Lazy Persistency: A High-Performing and Write-Efficient Software Persistency TechniqueMohammad Alshboul, James Tuck, Yan Solihin. 439-451 [doi]
• DHTM: Durable Hardware Transactional MemoryArpit Joshi, Vijay Nagarajan, Marcelo Cintra, Stratis Viglas. 452-465 [doi]
• Hardware Supported Permission Checks on Persistent Objects for Performance and ProgrammabilityTiancong Wang, Sakthikumaran Sambasivam, James Tuck. 466-478 [doi]
• RoboX: An End-to-End Solution to Accelerate Autonomous Control in RoboticsJacob Sacks, Divya Mahajan, Richard C. Lawson, Hadi Esmaeilzadeh. 479-490 [doi]
• DCS-ctrl: A Fast and Flexible Device-Control Mechanism for Device-Centric Server ArchitectureDongup Kwon, Jaehyung Ahn, Dongju Chae, Mohammadamin Ajdari, Jaewon Lee, Suheon Bae, Youngsok Kim, Jangwoo Kim. 491-504 [doi]
• Yukta: Multilayer Resource Controllers to Maximize EfficiencyRaghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas. 505-518 [doi]
• Exploring Predictive Replacement Policies for Instruction Cache and Branch Target BufferSamira Mirbagher Ajorpaz, Elba Garza, Sangam Jindal, Daniel A. Jiménez. 519-532 [doi]
• 2: Exploiting Temporal Redundancy in Live Computer VisionMark Buckler, Philip Bedoukian, Suren Jayasuriya, Adrian Sampson. 533-546 [doi]
• Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous VisionYuhao Zhu, Anand Samajdar, Matthew Mattina, Paul N. Whatmough. 547-560 [doi]
• Guaranteeing Local Differential Privacy on Ultra-Low-Power SystemsWoo-seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte, Pavan Kumar Hanumolu, Rakesh Kumar 0002. 561-574 [doi]
• Stitch: Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for WearablesCheng Tan, Manupa Karunaratne, Tulika Mitra, Li-Shiuan Peh. 575-587 [doi]
• Nonblocking Memory RefreshKate Nguyen, Kehan Lyu, Xianze Meng, Vilas Sridharan, Xun Jian. 588-599 [doi]
• Practical Memory Safety with RESTKanad Sinha, Simha Sethumadhavan. 600-611 [doi]
• Mitigating Wordline Crosstalk Using Adaptive Trees of CountersSeyed Mohammad Seyedzadeh, Alex K. Jones, Rami G. Melhem. 612-623 [doi]
• Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy EfficiencyMohammadkazem Taram, Ashish Venkat, Dean M. Tullsen. 624-637 [doi]
• Hiding Intermittent Information Leakage with Architectural Support for BlinkingAlric Althoff, Joseph McMahan, Luis Vega Gutierrez, Scott Davidson, Timothy Sherwood, Michael Bedford Taylor, Ryan Kastner. 638-649 [doi]
• GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial NetworksAmir Yazdanbakhsh, Kambiz Samadi, Nam Sung Kim, Hadi Esmaeilzadeh. 650-661 [doi]
• SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural NetworksVahideh Akhlaghi, Amir Yazdanbakhsh, Kambiz Samadi, Rajesh K. Gupta 0001, Hadi Esmaeilzadeh. 662-673 [doi]
• UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight RepetitionKartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher. 674-687 [doi]
• Energy-Efficient Neural Network Accelerator Based on Outlier-Aware Low-Precision ComputationEunhyeok Park, Dongyoung Kim, Sungjoo Yoo. 688-698 [doi]
• Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock FreedomAniruddh Ramrakhyani, Paul V. Gratz, Tushar Krishna. 699-711 [doi]
• TCEP: Traffic Consolidation for Energy-Proportional High-Radix NetworksGwangsun Kim, Hayoung Choi, John Kim. 712-725 [doi]
• Modular Routing Design for Chiplet-Based SystemsJieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natalie D. Enright Jerger, Gabriel H. Loh. 726-738 [doi]
• FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCsNachiket Kapre, Tushar Krishna. 739-751 [doi]
• Prediction Based Execution on Deep Neural NetworksMingcong Song, Jiechen Zhao, Yang Hu 0001, Jiaqi Zhang, Tao Li. 752-763 [doi]
• Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural NetworkHardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Vikas Chandra, Hadi Esmaeilzadeh. 764-775 [doi]
• Gist: Efficient Data Encoding for Deep Neural Network TrainingAnimesh Jain, Amar Phanishayee, Jason Mars, Lingjia Tang, Gennady Pekhimenko. 776-789 [doi]
• The Dark Side of DNN PruningReza Yazdani, Marc Riera, Jose-Maria Arnau, Antonio González 0001. 790-801 [doi]
• HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUsBhargava Gopireddy, Dimitrios Skarlatos, Wenjuan Zhu, Josep Torrellas. 802-815 [doi]
• RegMutex: Inter-Warp GPU Register Time-SharingFarzad Khorasani, Hodjat Asghari Esfeden, Amin Farmahini Farahani, Nuwan Jayasena, Vivek Sarkar. 816-828 [doi]
• The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality In GPUsNandita Vijaykumar, Eiman Ebrahimi, Kevin Hsieh, Phillip B. Gibbons, Onur Mutlu. 829-842 [doi]
• Generic System Calls for GPUsJán Veselý, Arkaprava Basu, Abhishek Bhattacharjee, Gabriel H. Loh, Mark Oskin, Steven K. Reinhardt. 843-856 [doi]