Abstract is missing.
- Workloads, Scalability, and QoS Considerations in CMP PlatformsDonald Newell. [doi]
- Performance Modeling and Analysis for AMD s High Performance MicroprocessorsLeslie Barnes. [doi]
- Accelerating Full-System Simulation through Characterizing and Predicting Operating System PerformanceSeongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer, Li Zhao, W. Cohen. 1-11 [doi]
- A Comparison of Two Approaches to Parallel Simulation of MultiprocessorsAndrew Over, Bill Clarke, Peter E. Strazdins. 12-22 [doi]
- PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural SimulatorMatt T. Yourst. 23-34 [doi]
- Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulationWenlong Li, Eric Li, Aamer Jaleel, Jiulong Shan, Yurong Chen, Qigang Wang, Ravi R. Iyer, Ramesh Illikkal, Yimin Zhang, Dong Liu, M. Liao, Wei Wei, Jinhua Du. 35-43 [doi]
- Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for OptimizationsYefim Shuf, Ian M. Steiner. 44-53 [doi]
- Performance Characterization of Decimal Arithmetic in Commercial Java WorkloadsMahesh Bhat, John Crawford, Ricardo Morin, Kumar Shiv. 54-61 [doi]
- Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec ApplicationsMauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero. 62-71 [doi]
- Combining Simulation and Virtualization through Dynamic SamplingAyose Falcón, Paolo Faraboschi, Daniel Ortega. 72-83 [doi]
- Phase-Guided Small-Sample SimulationJoshua L. Kihm, Samuel D. Strom, Daniel A. Connors. 84-93 [doi]
- DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power SavingJiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang, Howard David. 94-104 [doi]
- Last-Touch Correlated Data StreamingMichael Ferdman, Babak Falsafi. 105-115 [doi]
- Using Model Trees for Computer Architecture Performance Analysis of Software ApplicationsElMoustapha Ould-Ahmed-Vall, James Woodlee, Charles Yount, Kshitij A. Doshi, Seth Abraham. 116-125 [doi]
- Modeling and Single-Pass Simulation of CMP Cache Capacity and AccessibilityXudong Shi, Feiqi Su, Jih-Kwon Peir, Ye Xia, Zhen Yang. 126-135 [doi]
- Using Wavelet Domain Workload Execution Characteristics to Improve Accuracy, Scalability and Robustness in Program Phase AnalysisChang-Burm Cho, Tao Li. 136-145 [doi]
- Modeling and Characterizing Power Variability in Multicore ArchitecturesKe Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail. 146-157 [doi]
- Complete System Power Estimation: A Trickle-Down Approach Based on Performance EventsW. Lloyd Bircher, Lizy K. John. 158-168 [doi]
- An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded ArchitecturesWangyuan Zhang, Xin Fu, Tao Li, José A. B. Fortes. 169-178 [doi]
- Cross Binary Simulation PointsErez Perelman, Jeremy Lau, Harish Patil, Aamer Jaleel, Greg Hamerly, Brad Calder. 179-189 [doi]
- Reverse State Reconstruction for Sampled Microarchitectural SimulationPaul D. Bryan, Michel C. Rosier, Thomas M. Conte. 190-199 [doi]
- An Analysis of Performance Interference Effects in Virtual EnvironmentsYounggyun Koh, Rob C. Knauerhase, Paul Brett, Mic Bowman, Zhihua Wen, Calton Pu. 200-209 [doi]
- Performance Analysis of Cell Broadband Engine for High Memory Bandwidth ApplicationsDaniel Jiménez-González, Xavier Martorell, Alex Ramírez. 210-219 [doi]
- Benefits of I/O Acceleration Technology (I/OAT) in ClustersKarthikeyan Vaidyanathan, Dhabaleswar K. Panda. 220-229 [doi]
- CA-RAM: A High-Performance Memory Substrate for Search-Intensive ApplicationsSangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem. 230-241 [doi]
- Simplifying Active Memory Clusters by Leveraging Directory Protocol ThreadsDhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinrich. 242-253 [doi]