Abstract is missing.
- Bridging the energy-efficiency gap in a future of massive dataFred Chong. 1 [doi]
- BarrierPoint: Sampled simulation of multi-threaded applicationsTrevor E. Carlson, Wim Heirman, Kenzo Van Craeynest, Lieven Eeckhout. 2-12 [doi]
- Sources of error in full-system simulationAnthony Gutierrez, Joseph Pusdesris, Ronald G. Dreslinski, Trevor N. Mudge, Chander Sudanthi, Christopher D. Emmons, Mitchell Hayenga, Nigel C. Paver. 13-22 [doi]
- Exploiting spatial architectures for edit distance algorithmsJesmin Jahan Tithi, Neal Clayton Crago, Joel S. Emer. 23-34 [doi]
- A Top-Down method for performance analysis and counters architectureAhmad Yasin. 35-44 [doi]
- Moby: A mobile benchmark suite for architectural simulatorsYongbing Huang, Zhongbin Zha, Mingyu Chen, Lixin Zhang 0002. 45-54 [doi]
- The design space of ultra-low energy asymmetric cryptographyAndrew D. Targhetta, Donald E. Owen, Paul V. Gratz. 55-65 [doi]
- Optimized hardware for suboptimal software: The case for SIMD-aware benchmarksJuan M. Cebrian, Magnus Jahre, Lasse Natvig. 66-75 [doi]
- Applying the roofline modelGeorg Ofenbeck, Ruedi Steinmann, Victoria Caparros, Daniele G. Spampinato, Markus Püschel. 76-85 [doi]
- Extending statistical cache models to support detailed pipeline simulatorsNikos Nikoleris, David Eklov, Erik Hagersten. 86-95 [doi]
- Modeling cache coherence misses on multicoresXiaoyue Pan, Bengt Jonsson. 96-105 [doi]
- Manifold: A parallel simulation framework for multicore systemsJun Wang, Jesse G. Beu, Rishiraj A. Bheda, Tom Conte, Zhenjiang Dong, Chad D. Kersey, Mitchelle Rasquinha, George F. Riley, William J. Song, He Xiao, Peng Xu, Sudhakar Yalamanchili. 106-115 [doi]
- PriME: A parallel and distributed simulator for thousand-core chipsYaosheng Fu, David Wentzlaff. 116-125 [doi]
- A study of Thread Level Parallelism on mobile devicesCao Gao, Anthony Gutierrez, Ronald G. Dreslinski, Trevor N. Mudge, Krisztián Flautner, Geoffrey Blake. 126-127 [doi]
- Transforming Java programs for concurrency using Double-Checked Locking patternKazuaki Ishizaki, Shahrokh Daijavad, Toshio Nakatani. 128-129 [doi]
- ParTejas: A parallel simulator for multicore processorsGeetika Malhotra, Pooja Aggarwal, Abhishek Sagar, Smruti R. Sarangi. 130-131 [doi]
- Power modeling and other new features in the Graphite simulatorGeorge Kurian, Sabrina M. Neuman, George Bezerra, Anthony Giovinazzo, Srinivas Devadas, Jason E. Miller. 132-134 [doi]
- Accelerating network-on-chip simulation via samplingWenbo Dai, Natalie D. Enright Jerger. 135-136 [doi]
- A case for resource efficient prefetching in multicoresMuneeb Khan, Andreas Sandberg, Erik Hagersten. 137-138 [doi]
- Evaluating trace aggregation for performance visualization of large distributed systemsRobin Lamarche-Perrin, Lucas Mello Schnorr, Jean-Marc Vincent, Yves Demazeau. 139-140 [doi]
- Reverse engineering of cache replacement policies in Intel microprocessors and their evaluationAndreas Abel 0002, Jan Reineke. 141-142 [doi]
- Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architecturesWilliam J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili. 143-144 [doi]
- Characterizing the latency hiding ability of GPUsShin-Ying Lee, Carole-Jean Wu. 145-146 [doi]
- Life lessons and datacenter performance analysisAmer Diwan. 147 [doi]
- A software based profiling method for obtaining speedup stacks on commodity multi-coresDavid Eklov, Nikos Nikoleris, Erik Hagersten. 148-157 [doi]
- MIAMI: A framework for application performance diagnosisGabriel Marin, Jack Dongarra, Daniel Terpstra. 158-168 [doi]
- Quality Time: A simple online technique for quantifying multicore execution efficiencyAnshuman Gupta, Jack Sampson, Michael Bedford Taylor. 169-179 [doi]
- Variability of data dependences and control flowTobias J. K. Edler von Koch, Björn Franke. 180-189 [doi]
- NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloadsSeth H. Pugsley, Jeffrey Jestes, HuiHui Zhang, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li. 190-200 [doi]
- Simulating DRAM controllers for future system architecture explorationAndreas Hansson, Neha Agarwal, Aasheesh Kolli, Thomas F. Wenisch, Aniruddha N. Udipi. 201-210 [doi]
- Energy-efficient reconfigurable cache architectures for accelerator-enabled embedded systemsAmin Farmahini Farahani, Nam Sung Kim, Katherine Morrow. 211-220 [doi]
- GPU-Qin: A methodology for evaluating the error resilience of GPGPU applicationsBo Fang, Karthik Pattabiraman, Matei Ripeanu, Sudhanva Gurumurthi. 221-230 [doi]
- Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUsChao Li, Yi Yang, Hongwen Dai, Shengen Yan, Frank Mueller, Huiyang Zhou. 231-242 [doi]