Abstract is missing.
- Hierarchical Computation in the SPMD Programming ModelAmir Kamil, Katherine A. Yelick. 3-19 [doi]
- Porting Applications with OpenMP Using Similarity AnalysisWei Ding, Oscar Hernandez, Tony Curtis, Barbara M. Chapman. 20-35 [doi]
- Task-Aware Optimization of Dynamic Fractional PermissionsChristoph M. Angerer. 39-54 [doi]
- Near Optimal Work-Stealing Tree Scheduler for Highly Irregular Data-Parallel WorkloadsAleksandar Prokopec, Martin Odersky. 55-86 [doi]
- OpenCL Task Partitioning in the Presence of GPU ContentionDominik Grewe, Zheng Wang, Michael F. P. O'Boyle. 87-101 [doi]
- Compiling a High-Level Directive-Based Programming Model for GPGPUsXiaonan Tian, Rengan Xu, Yonghong Yan 0001, Zhifeng Yun, Sunita Chandrasekaran, Barbara M. Chapman. 105-120 [doi]
- Separate Compilation in a Language-Integrated Heterogeneous EnvironmentMike Murphy, Jaydeep Marathe, Girish Bharambe, Sean Lee, Vinod Grover. 121-135 [doi]
- Parametric GPU Code Generation for Affine Loop ProgramsAthanasios Konstantinidis, Paul H. J. Kelly, J. Ramanujam, P. Sadayappan. 136-151 [doi]
- OSCAR Compiler Controlled Multicore Power Reduction on Android PlatformHideo Yamamoto, Tomohiro Hirano, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara. 155-168 [doi]
- Folklore Confirmed: Compiling for Speed = Compiling for EnergyTomofumi Yuki, Sanjay V. Rajopadhye. 169-184 [doi]
- Effectively Recognize Ad hoc Synchronizations with Static AnalysisLe Yin. 187-201 [doi]
- AntSM: Efficient Debugging for Shared Memory Parallel ProgramsJae-Woo Lee, Samuel P. Midkiff. 202-216 [doi]
- DRIFT: Decoupled CompileR-Based Instruction-Level Fault-ToleranceKonstantina Mitropoulou, Vasileios Porpodas, Marcelo Cintra. 217-233 [doi]
- Optimizing the LU Factorization for Energy Efficiency on a Many-Core ArchitectureElkin Garcia, Jaime Arteaga, Robert S. Pavel, Guang R. Gao. 237-251 [doi]
- An Input-Adaptive Algorithm for High Performance Sparse Fast Fourier TransformShuo Chen, Xiaoming Li. 252-271 [doi]
- Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW ProcessorsVasileios Porpodas, Marcelo Cintra. 275-291 [doi]
- Compile Time Modeling of Off-Chip Memory Bandwidth for Parallel LoopsMunara Tolubaeva, Yonghong Yan 0001, Barbara M. Chapman. 292-306 [doi]
- Compiler Optimizations for Non-contiguous Remote Data MovementTimo Schneider, Robert Gerstenberger, Torsten Hoefler. 307-321 [doi]
- Combining Lock Inference with Lock-Based Software Transactional MemoryStefan Kempf, Ronald Veldema, Michael Philippsen. 325-341 [doi]
- Speculative Execution of Parallel Programs with Precise Exception Semantics on GPUsAkihiro Hayashi, Max Grossman, Jisheng Zhao, Jun Shirako, Vivek Sarkar. 342-356 [doi]