Table of Contents

• An Enhanced Profiling Framework for the Analysis and Development of Parallel Primitives for GPUsNicola Bombieri, Federico Busato, Franco Fummi. 1-8 [doi]
• Managing the Latency of Data-Dependent Tasks in Embedded Streaming ApplicationsXuanKhanh Do, Stéphane Louise, Albert Cohen 0001. 9-16 [doi]
• Measuring Predictability of Nvidia's GPU Schedulers: Application to the Summation ProblemDavid Defour. 17-24 [doi]
• Hierarchical Library Based Power Estimator for Versatile FPGAsHao Liang, Yi-Chung Chen, Tao Luo, Wei Zhang, Hai Li, Bingsheng He. 25-32 [doi]
• A Scalable and Fast Microprocessor Design Space Exploration MethodologyLei Wang, YuXing Tang, Yu Deng, Fangyan Qin, Qiang Dou, Guangda Zhang, Feipeng Zhang. 33-40 [doi]
• Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny ChipsHiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. 41-48 [doi]
• FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core SystemsRyohei Kobayashi, Kenji Kise. 49-56 [doi]
• Why Race-to-Finish is Energy-Inefficient for Continuous Multimedia WorkloadsKristoffer Robin Stokke, Håkon Kvale Stensland, Pål Halvorsen, Carsten Griwodz. 57-64 [doi]
• Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and ResearchEri Ogawa, Yuki Matsuda, Tomohiro Misono, Ryohei Kobayashi, Kenji Kise. 65-72 [doi]
• A CGRA-Based Approach for Accelerating Convolutional Neural NetworksMasakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima. 73-80 [doi]
• FPU Speedup Estimation for Task Placement Optimization on Asymmetric Multicore DesignsAlexandre Aminot, Yves Lhuillier, Andrea Castagnetti, Henri-Pierre Charles. 81-87 [doi]
• On the Load Balancing Techniques for GPU Applications Based on Prefix-ScanFederico Busato, Nicola Bombieri. 88-95 [doi]
• Abstracting Parallel Programming and Its Analysis Towards Framework Independent DevelopmentOliver Jakob Arndt, Tile Lefherz, Holger Blume. 96-103 [doi]
• Towards Automatic Code Generation of Run-Time Power Management for Embedded Systems Using Formal MethodsAsieh Salehi Fathabadi, Luis Alfonso Maeda-Nunez, Michael J. Butler, Bashir M. Al-Hashimi, Geoff V. Merrett. 104-111 [doi]
• GPU Particle Swarm Optimization Applied to Travelling Salesman ProblemOlfa Bali, Walid Elloumi, Pavel Krömer, Adel M. Alimi. 112-119 [doi]
• Energy-Aware Bio-signal Compressed Sensing Reconstruction: FOCUSS on the WBSN-GatewayDaniele Bortolotti, Andrea Bartolini, Mauro Mangia, Riccardo Rovatti, Gianluca Setti, Luca Benini. 120-126 [doi]
• Top-Down Profiling of Application Specific Many-core Neuromorphic PlatformsGianvito Urgese, Francesco Barchi, Enrico Macii. 127-134 [doi]
• Predictable Application Mapping for Manycore Real-Time and Cyber-Physical SystemsAnil Kanduri, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen. 135-142 [doi]
• Automatic Runtime Customization for Variability Awareness on Multicore PlatformsGasser Ayad, Ramakrishna Nittala, Romain Lemaire. 143-150 [doi]
• Dynamic VC Organization for Efficient NoC CommunicationMasoud Oveis Gharan, Gul N. Khan. 151-158 [doi]
• A Performance Prediction for Automatic Placement of Heterogeneous Workloads on Many-coresNicolas Benoit, Stéphane Louise. 159-166 [doi]
• Adaptive Time-Based Least Memory Intensive SchedulingAmr Saleh Elhelw, Ali El-Moursy, Hossam Ali Hassan Fahmy. 167-174 [doi]
• Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOIGregor Sievers, Julian Daberkow, Johannes Ax, Martin Flasskamp, Wayne Kelly, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001. 175-181 [doi]
• Lighting the Dark-Silicon 3D Chip Multi-processors by Exploiting Heterogeneity in Cache HierarchyAshkan Sadeghi, Kaamran Raahemifar, Mahmood Fathy, Arghavan Asad. 182-186 [doi]
• Memory Access Analysis of Many-core System with Abundant BandwidthChuan Tang, Dan Liu, Zuocheng Xing, Peng Yang, Zhe Wang, Jiang Xu. 187-194 [doi]
• CLTune: A Generic Auto-Tuner for OpenCL KernelsCedric Nugteren, Valeriu Codreanu. 195-202 [doi]
• Enhancement of Incremental Performance Parameter Estimation on ppOpen-ATRiku Murata, Jun Irie, Akihiro Fujii, Teruo Tanaka, Takahiro Katagiri. 203-210 [doi]
• Improving Auto-Tuning Convergence Times with Dynamically Generated Predictive Performance ModelsJames Price, Simon McIntosh-Smith. 211-218 [doi]
• The Approximate Discrete Radon Transform: A Case Study in Auto-Tuning of OpenCL ImplementationsH. Martin Bücker, Ralf Seidler, David Neuhäuser, Tobias Beier. 219-226 [doi]
• FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip SystemsMichael Conrad Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah. 227-234 [doi]
• Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip SystemsAchraf Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah. 235-242 [doi]
• Communication Aware Design Method for Optical Network-on-ChipJohanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cedric Killian, Daniel Chillet, Hui Li, Ian O'Connor, Olivier Sentieys. 243-250 [doi]
• On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip ArchitecturesMichael Opoku Agyeman, Ji-Xiang Wan, Quoc-Tuan Vien, Wen Zong, Alex Yakovlev, Kenneth Tong, Terrence S. T. Mak. 251-258 [doi]
• 3D Shared Bus Architecture Using Inductive Coupling InterconnectAkio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano. 259-266 [doi]
• Cross by Pass-Mesh Architecture for On-chip CommunicationUsman Ali Gulzari, Sheraz Anjum, Shahrukh Agha. 267-274 [doi]
• Implementation and Modeling for High-performance I/O Hub Used in SPARC M7 Processor-Based ServersJohn R. Feehrer, Jeffry Hughes, Hugh Kurth, David Pabisz, Peter Yakutis. 275-282 [doi]
• Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault ModelElmira Karimi, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mahmoud Tabandeh, Pasi Liljeberg, Zainalabedin Navabi. 283-288 [doi]
• ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core AcceleratorsGiuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini. 289-296 [doi]
• Enabling Scalable and Fine-Grained Nested Parallelism on Embedded Many-coresAlessandro Capotondi, Andrea Marongiu, Luca Benini. 297-304 [doi]
• The Network Performance Analysis Platform and Its Application to Network Buffer Evaluation of the Embedded SystemYuichi Sakurai, Ken-ichi Shimbo, Tadanobu Toba, Hideki Osaka. 305-312 [doi]