Abstract is missing.
- Code Generation of Graph-Based Vision Processing for Multiple CUDA Cores SoC Jetson TXElishai Ezra Tsur, Elyassaf Madar, Natan Danan. 1-7 [doi]
- An FPGA Scalable Parallel Viterbi DecoderYosi Ben-Asher, Vladislav Tartakovsky, Katrina Portman, Orr Zilberman, Avishi Hadar. 8-15 [doi]
- An Efficient Parallel Hardware Scheme for Solving the N-Queens ProblemYuuma Azuma, Hayato Sakagami, Kenji Kise. 16-22 [doi]
- Simplified Quadcopter Simulation Model for Spike-Based Hardware PID Controller using SystemC-AMSShunsuke Mie, Yuichi Okuyama, Hiroaki Saito. 23-27 [doi]
- Unifying Wire and Time Scheduling for Highlevel SynthesisYosi Ben-Asher, Irina Lipov. 28-35 [doi]
- IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAsKhoa Dang Pham, Edson L. Horta, Dirk Koch, Anuj Vaishnav, Thomas Kuhn. 36-43 [doi]
- On-Chip Lifetime Prediction for Dependable Many-Processor SoCs Based on Data FusionGhazanfar Ali, Jerrin Pathrose, Hans G. Kerkhoff. 44-51 [doi]
- Design Features of Analog-to-Digital Solutions for the Tracking Detector Readout ElectronicsAleksandr Kostrov, Viktor Stempitsky, Artur Borovik, Vladimir Tchekhovsky. 52-56 [doi]
- Bluetooth Low Energy Based Indoor Positioning on iOS PlatformSon Ngoc Duong, Anh Vu-Tuan Trinh, Thai-Mai Dinh. 57-63 [doi]
- A Practical High Efficiency Video Coding Solution for Visual Sensor Network using Raspberry Pi PlatformThao Nguyen Thi Huong, Huy Phi Cong, Xiem HoangVan, Tien Huu Vu. 64-68 [doi]
- Adaptive Long-Term Reference Selection for Efficient Scalable Surveillance Video CodingXiem HoangVan, Le Dao Thi Hue, Giap PhamVan. 69-73 [doi]
- Light Field Image Coding for Efficient RefocusingVinh Van Duong, Thuong Nguyen Canh, Byeungwoo Jeon. 74-78 [doi]
- Adaptive Genetic Algorithm for Improving Prediction Accuracy of a Multi-Criteria Recommender SystemMohamed Hamada, Abdulsalam Latifat, Mohammed Hassan. 79-86 [doi]
- A Fuzzy-Based Approach for Modelling Preferences of Users in Multi-Criteria Recommender SystemsMohamed Hamada, Nkiruka Bridget Odu, Mohammed Hassan. 87-94 [doi]
- A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS ProcessPhuc-Vinh Nguyen, Thi-Thu-Trang Tran, Phuoc-Loc Diep, Duc-Hung Le. 95-100 [doi]
- A Novel Task-to-Processor Assignment Approach for Optimal Multiprocessor Real-Time SchedulingDoan Duy, Kiyofumi Tanaka. 101-108 [doi]
- Multikernel Design and Implementation for Improving Responsiveness of Aperiodic TasksHidehito Yabuuchi, Shinichi Awamoto, Hiroyuki Chishiro, Shinpei Kato. 109-116 [doi]
- Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing ProcessorKazuhiko Komatsu, Takumi Kishitani, Masayuki Sato 0001, Akihiro Musa, Hiroaki Kobayashi. 117-124 [doi]
- Communication-Avoiding Tile QR Decomposition on CPU/GPU Heterogeneous Cluster SystemMasatoshi Takayanagi, Tomohiro Suzuki. 125-131 [doi]
- Freeze-Safe IoT Hibernation using Power Profile Monitor Based on Communication-Centric Auto-TuningHyeongyun Moon, Jeonghun Cho, Daejin Park. 132-137 [doi]
- In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory ArchitecturesLeonard Masing, Akshay Srivatsa, Fabian KreB, Nidhi Anantharajaiah, Andreas Herkersdorf, Jürgen Becker. 138-145 [doi]
- Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip SystemsAkram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. 146-153 [doi]
- Parity-Based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip CommunicationKhanh N. Dang, Xuan-Tu Tran. 154-161 [doi]
- MARTE and IP-XACT Based Approach for Run-Time Scalable NoCHiliwi Leake Kidane, El-Bay Bourennane. 162-167 [doi]
- Scalable Dynamic Task Scheduling on Adaptive Many-CoreVanchinathan Venkataramani, Anuj Pathania, Muhammad Shafique 0001, Tulika Mitra, Jörg Henkel. 168-175 [doi]
- On the Complexity of Mapping Feasibility in Many-Core ArchitecturesTobias Schwarzer, Sascha Roloff, Valentina Richthammer, Rami Khaldi, Stefan Wildermann, Michael Glaß, Jürgen Teich. 176-183 [doi]
- On the Representation of Mappings to MulticoresAndres Goens, Christian Menard, Jerónimo Castrillón. 184-191 [doi]
- Evaluation of Performance and Fault Containment in AUTOSAR Micro-ECUs on a Multi-Core ProcessorMoises Urbina, Roman Obermaisser. 192-200 [doi]
- Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output RecordsElsayed A. Elsayed, Kenji Kise. 201-208 [doi]
- On-Line Cost-Aware Workflow Allocation in Heterogeneous Computing EnvironmentsIncheon Paik, Yuji Ishizuka, Quang-Minh Do, Wuhui Chen. 209-216 [doi]
- FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSATKenji Kanazawa, Shaowei Cai. 217-224 [doi]
- VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration LimitationsTrong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham. 225-232 [doi]
- An Efficient Hardware Implementation of Activation Functions Using Stochastic Computing for Deep Neural NetworksVan Tinh Nguyen, Tieu-Khanh Luong, Han Le Duc, Van-Phuc Hoang. 233-236 [doi]
- Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared AccumulatorsTakumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki. 237-243 [doi]
- Designing Compact Convolutional Neural Network for Embedded Stereo Vision SystemsMohammad Loni, Amin Majd, Abdolah Loni, Masoud Daneshtalab, Mikael Sjödin, Elena Troubitsyna. 244-251 [doi]