Abstract is missing.
- PFetch: software prefetching exploiting temporal predictability of memory access streamsJaydeep Marathe, Frank Mueller 0001. 1-8 [doi]
- Modeling of cache access behavior based on Zipf's lawIsao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 9-15 [doi]
- Zero loads: canceling load requests by tracking zero valuesMafijul Md. Islam, Per Stenström. 16-23 [doi]
- A shared cache for a chip multi vector processorAkihiro Musa, Yoshiei Sato, Takashi Soga, Koki Okabe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 24-29 [doi]
- A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 cachesHyunhee Kim, Sungjun Youn, Jihong Kim 0001. 30-37 [doi]
- Predictable dynamic instruction scratchpad for simultaneous multithreaded processorsStefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer. 38-45 [doi]
- Exploiting multithreaded architectures to improve the hash join operationLayali K. Rashid, Wessam M. Hassanein, Moustafa A. Hammad. 46-53 [doi]
- Accurate system-level performance modeling and workload characterization for mobile internet devicesMitchell Hayenga, Chander Sudanthi, Mrinmoy Ghosh, Prakash Ramrakhyani, Nigel C. Paver. 54-60 [doi]
- WormBench: a configurable workload for evaluating transactional memory systemsFerad Zyulkyarov, Adrián Cristal, Sanja Cvijic, Eduard Ayguadé, Mateo Valero, Osman S. Unsal, Tim Harris 0001. 61-68 [doi]
- Version management alternatives for hardware transactional memoryMarc Lupon, Grigorios Magklis, Antonio González 0001. 69-76 [doi]
- Evaluation of memory performance on the cell BE with the SARC programming modelRoger Ferrer, Marc González, Federico Silla, Xavier Martorell, Eduard Ayguadé. 77-84 [doi]